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Found 13 papers, 5 papers with code
An Efficient Training Framework for Reversible Neural Architectures
In this work, we formulate the decision problem for reversible operators with training time as the objective function and memory usage as the constraint.
Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance
This paper presents a comparative analysis of total cost of ownership (TCO) and performance between domain-adapted large language models (LLM) and state-of-the-art (SoTA) LLMs , with a particular emphasis on tasks related to coding assistance for chip design.
ChipNeMo: Domain-Adapted LLMs for Chip Design
ChipNeMo aims to explore the applications of large language models (LLMs) for industrial chip design.
VerilogEval: Evaluating Large Language Models for Verilog Code Generation
The increasing popularity of large language models (LLMs) has paved the way for their application in diverse domains.
An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design
These synthetic mask images will augment the original limited training dataset used to finetune the lithography model for improved performance.
Delving into Effective Gradient Matching for Dataset Condensation
In this work, we delve into the gradient matching method from a comprehensive perspective and answer the critical questions of what, how, and where to match.
RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL
To address the challenge, we present RobustAnalog, a robust circuit design framework that involves the variation information in the optimization process.
ELight: Enabling Efficient Photonic In-Memory Neurocomputing with Life Enhancement
With the recent advances in optical phase change material (PCM), photonic in-memory neurocomputing has demonstrated its superiority in optical neural network (ONN) designs with near-zero static power consumption, time-of-light latency, and compact footprint.
RoDesigner: Variation-Aware Optimization for Robust Analog Design with Multi-Task RL
Specifically, circuit optimizations under different variations are considered as a set of tasks.
Towards Memory-Efficient Neural Networks via Multi-Level in situ Generation
Deep neural networks (DNN) have shown superior performance in a variety of tasks.
Optimizer Fusion: Efficient Training with Better Locality and Parallelism
Machine learning frameworks adopt iterative optimizers to train neural networks.
SqueezeLight: Towards Scalable Optical Neural Networks with Multi-Operand Ring Resonators
Optical neural networks (ONNs) have demonstrated promising potentials for next-generation artificial intelligence acceleration with ultra-low latency, high bandwidth, and low energy consumption.
DC2Anet: Generating Lumbar Spine MR Images from CT Scan Data Based on Semi-Supervised Learning
In this paper, we propose a method for estimating lumbar spine MR images based on CT images using a novel objective function and a dual cycle-consistent adversarial network (DC2Anet) with semi-supervised learning.
