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Found 14 papers, 1 papers with code
Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance
This paper presents a comparative analysis of total cost of ownership (TCO) and performance between domain-adapted large language models (LLM) and state-of-the-art (SoTA) LLMs , with a particular emphasis on tasks related to coding assistance for chip design.
Optimizing Predictive AI in Physical Design Flows with Mini Pixel Batch Gradient Descent
Exploding predictive AI has enabled fast yet effective evaluation and decision-making in modern chip physical design flows.
BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation
Boolean algebraic manipulation is at the core of logic synthesis in Electronic Design Automation (EDA) design flow.
ChipNeMo: Domain-Adapted LLMs for Chip Design
ChipNeMo aims to explore the applications of large language models (LLMs) for industrial chip design.
VerilogEval: Evaluating Large Language Models for Verilog Code Generation
The increasing popularity of large language models (LLMs) has paved the way for their application in diverse domains.
An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design
These synthetic mask images will augment the original limited training dataset used to finetune the lithography model for improved performance.
TAG: Learning Circuit Spatial Embedding From Layouts
Analog and mixed-signal (AMS) circuit designs still rely on human design expertise.
Large Scale Mask Optimization Via Convolutional Fourier Neural Operator and Litho-Guided Self Training
Machine learning techniques have been extensively studied for mask optimization problems, aiming at better mask printability, shorter turnaround time, better mask manufacturability, and so on.
Generic Lithography Modeling with Dual-band Optics-Inspired Neural Networks
Lithography simulation is a critical step in VLSI design and optimization for manufacturability.
GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement
In this paper, we present GATSPI, a novel GPU accelerated logic gate simulator that enables ultra-fast power estimation for industry sized ASIC designs with millions of gates.
NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
High quality standard cell layout automation in advanced technology nodes is still challenging in the industry today because of complex design rules.
VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference
4-bit weights and 8-bit activations achieve near-full-precision accuracy for both BERT-base and BERT-large on SQuAD while reducing area by 26% compared to an 8-bit baseline.
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network
Moreover, the proposed CNN model is general and transferable to different designs.
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning
Experimental results on benchmark circuits show that our approach achieves 25% improvement in design quality or 37% reduction in sampling cost compared to random forest method, which is the kernel of a highly cited previous work.
