Search Results for author:
Found 12 papers, 3 papers with code
Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS
We present a technique that allows searching for training proxies that reduce the cost of benchmark construction by significant margins, making it possible to construct realistic NAS benchmarks for large-scale datasets.
PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
Based on the formulation, we propose PANDA, an innovative architecture-level solution that combines the advantages of analytical and ML power models.
EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research
The application of Machine Learning (ML) in Electronic Design Automation (EDA) for Very Large-Scale Integration (VLSI) design has garnered significant research attention.
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
In this work, we propose an open-source benchmark named RTLLM, for generating design RTL with natural language instructions.
Intelligent Circuit Design and Implementation with Machine Learning
In this dissertation, I present multiple fast yet accurate ML models covering a wide range of chip design stages from the register-transfer level (RTL) to sign-off, solving primary chip-design problems about power, timing, interconnect, IR drop, routability, and design flow tuning.
Towards Collaborative Intelligence: Routability Estimation based on Decentralized Private Data
To further strengthen the results, we co-design a customized ML model FLNet and its personalization under the decentralized training scenario.
The Dark Side: Security Concerns in Machine Learning for EDA
The growing IC complexity has led to a compelling need for design efficiency improvement through new electronic design automation (EDA) methodologies.
Automatic Routability Predictor Development Using Neural Architecture Search
The rise of machine learning technology inspires a boom of its applications in electronic design automation (EDA) and helps improve the degree of automation in chip designs.
Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation
Net length is a key proxy metric for optimizing timing and power across various stages of a standard digital design flow.
Fast IR Drop Estimation with Machine Learning
IR drop constraint is a fundamental requirement enforced in almost all chip designs.
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning
Experimental results on benchmark circuits show that our approach achieves 25% improvement in design quality or 37% reduction in sampling cost compared to random forest method, which is the kernel of a highly cited previous work.
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network
Moreover, the proposed CNN model is general and transferable to different designs.
