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Found 24 papers, 11 papers with code
QuantumSEA: In-Time Sparse Exploration for Noise Adaptive Quantum Circuits
To address these two pain points, we propose QuantumSEA, an in-time sparse exploration for noise-adaptive quantum circuits, aiming to achieve two key objectives: (1) implicit circuits capacity during training - by dynamically exploring the circuit's sparse connectivity and sticking a fixed small number of quantum gates throughout the training which satisfies the coherence time and enjoy light noises, enabling feasible executions on real quantum devices; (2) noise robustness - by jointly optimizing the topology and parameters of quantum circuits under real device noise models.
DGR: Tackling Drifted and Correlated Noise in Quantum Error Correction via Decoding Graph Re-weighting
By counting the occurrences of edges and edge pairs in decoded matchings, we can statistically estimate the up-to-date probabilities of each edge and the correlations between them.
Transformer-QEC: Quantum Error Correction Code Decoding with Transferable Transformers
Quantum Error Correction (QEC) mitigates this by employing redundancy, distributing quantum information across multiple data qubits and utilizing syndrome qubits to monitor their states for errors.
RobustState: Boosting Fidelity of Quantum State Preparation via Noise-Aware Variational Training
Arbitrary state preparation algorithms can be broadly categorized into arithmetic decomposition (AD) and variational quantum state preparation (VQSP).
SnCQA: A hardware-efficient equivariant quantum convolutional circuit architecture
We propose SnCQA, a set of hardware-efficient variational circuits of equivariant quantum convolutional circuits respective to permutation symmetries and spatial lattice symmetries with the number of qubits $n$.
QuEst: Graph Transformer for Quantum Circuit Reliability Estimation
Specifically, the TorchQuantum library also supports using data-driven ML models to solve problems in quantum system research, such as predicting the impact of quantum noise on circuit fidelity and improving the quantum circuit compilation efficiency.
NAPA: Intermediate-level Variational Native-pulse Ansatz for Variational Quantum Algorithms
Therefore, we propose NAPA, a native-pulse ansatz generator framework for VQAs.
RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL
To address the challenge, we present RobustAnalog, a robust circuit design framework that involves the variation information in the optimization process.
Enable Deep Learning on Mobile Devices: Methods, Systems, and Applications
Deep neural networks (DNNs) have achieved unprecedented success in the field of artificial intelligence (AI), including computer vision, natural language processing and speech recognition.
QOC: Quantum On-Chip Training with Parameter Shift and Gradient Pruning
Nevertheless, we find that due to the significant quantum errors (noises) on real machines, gradients obtained from naive parameter shift have low fidelity and thus degrading the training accuracy.
Similarity-based Gray-box Adversarial Attack Against Deep Face Recognition
This technique applies to both white-box and gray-box attacks against authentication systems that determine genuine or imposter users using the dissimilarity score.
QuantumNAT: Quantum Noise-Aware Training with Noise Injection, Quantization and Normalization
Furthermore, to improve the robustness against noise, we propose noise injection to the training process by inserting quantum error gates to PQC according to realistic noise models of quantum hardware.
RoDesigner: Variation-Aware Optimization for Robust Analog Design with Multi-Task RL
Specifically, circuit optimizations under different variations are considered as a set of tasks.
Towards Efficient On-Chip Training of Quantum Neural Networks
The results demonstrate that our on-chip training achieves over 90% and 60% accuracy for 2-class and 4-class image classification tasks.
QuantumNAS: Noise-Adaptive Search for Robust Quantum Circuits
Extensively evaluated with 12 QML and VQE benchmarks on 14 quantum computers, QuantumNAS significantly outperforms baselines.
SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
Inspired by the high redundancy of human languages, we propose the novel cascade token pruning to prune away unimportant tokens in the sentence.
Searching Efficient 3D Architectures with Sparse Point-Voxel Convolution
Self-driving cars need to understand 3D scenes efficiently and accurately in order to drive safely.
Ranked #1 on
Robust 3D Semantic Segmentation
on SemanticKITTI-C
HAT: Hardware-Aware Transformers for Efficient Natural Language Processing
To enable low-latency inference on resource-constrained hardware platforms, we propose to design Hardware-Aware Transformers (HAT) with neural architecture search.
Ranked #21 on
Machine Translation
on WMT2014 English-French
MicroNet for Efficient Language Modeling
In this paper, we provide the winning solution to the NeurIPS 2019 MicroNet Challenge in the language modeling track.
GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning
Our transferable optimization method makes transistor sizing and design porting more effective and efficient.
SpArch: Efficient Architecture for Sparse Matrix Multiplication
We then propose a condensed matrix representation that reduces the number of partial matrices by three orders of magnitude and thus reduces DRAM access by 5. 4x.
Hardware Architecture Distributed, Parallel, and Cluster Computing
Park: An Open Platform for Learning-Augmented Computer Systems
We present Park, a platform for researchers to experiment with Reinforcement Learning (RL) for computer systems.
Learning to Design Circuits
We propose Learning to Design Circuits (L2DC) to leverage reinforcement learning that learns to efficiently generate new circuits data and to optimize circuits.
AMC: AutoML for Model Compression and Acceleration on Mobile Devices
Model compression is a critical technique to efficiently deploy neural network models on mobile devices which have limited computation resources and tight power budgets.
