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Found 25 papers, 1 papers with code
EventF2S: Asynchronous and Sparse Spiking AER Framework using Neuromorphic-Friendly Algorithm
Bio-inspired Address Event Representation (AER) sensors have attracted significant popularity owing to their low power consumption, high sparsity, and high temporal resolution.
RAMAN: A Re-configurable and Sparse tinyML Accelerator for Inference on Edge
In this paper, we present RAMAN, a Re-configurable and spArse tinyML Accelerator for infereNce on edge, architected to exploit the sparsity to reduce area (storage), power as well as latency.
Neuromorphic Computing with AER using Time-to-Event-Margin Propagation
Address-Event-Representation (AER) is a spike-routing protocol that allows the scaling of neuromorphic and spiking neural network (SNN) architectures to a size that is comparable to that of digital neural network architectures.
Multiplierless In-filter Computing for tinyML Platforms
Wildlife conservation using continuous monitoring of environmental factors and biomedical classification, which generate a vast amount of sensor data, is a challenge due to limited bandwidth in the case of remote monitoring.
Theoretical Insight into Batch Normalization: Data Dependant Auto-Tuning of Regularization Rate
Batch normalization is widely used in deep learning to normalize intermediate activations.
Process, Bias and Temperature Scalable CMOS Analog Computing Circuits for Machine Learning
Analog computing is attractive compared to digital computing due to its potential for achieving higher computational density and higher energy efficiency.
Bias-Scalable Near-Memory CMOS Analog Processor for Machine Learning
In this paper, we demonstrate the implementation of bias-scalable approximate analog computing circuits using the generalization of the margin-propagation principle called shape-based analog computing (S-AC).
In-filter Computing For Designing Ultra-light Acoustic Pattern Recognizers
We present a novel in-filter computing framework that can be used for designing ultra-light acoustic classifiers for use in smart internet-of-things (IoTs).
Multiplierless MP-Kernel Machine For Energy-efficient Edge Devices
We present a novel framework for designing multiplierless kernel machines that can be used on resource-constrained platforms like intelligent edge devices.
Event-LSTM: An Unsupervised and Asynchronous Learning-based Representation for Event-based Data
Compared to competing supervised approaches, ours is a task-agnostic approach ideally suited for the event domain, where task specific labeled data is scarce.
A Neuromorphic Proto-Object Based Dynamic Visual Saliency Model with an FPGA Implementation
The ability to attend to salient regions of a visual scene is an innate and necessary preprocessing step for both biological and engineered systems performing high-level visual tasks (e. g. object detection, tracking, and classification).
Real-Time Object Detection and Localization in Compressive Sensed Video on Embedded Hardware
Though cameras that perform compressive sensing save a lot of bandwidth at the time of sampling and minimize the memory required to store videos, we cannot do much in terms of processing until the videos are reconstructed to the original frames.
EvAn: Neuromorphic Event-based Anomaly Detection
Event-based cameras are bio-inspired novel sensors that asynchronously record changes in illumination in the form of events, thus resulting in significant advantages over conventional cameras in terms of low power utilization, high dynamic range, and no motion blur.
Multiplierless and Sparse Machine Learning based on Margin Propagation Networks
This is because at the fundamental level, neural network and machine learning operations extensively use MVM operations and hardware compilers exploit the inherent parallelism in MVM operations to achieve hardware acceleration on GPUs and FPGAs.
A Compressive Sensing Video dataset using Pixel-wise coded exposure
The first one is sparsity which requires the signal to be sparse in some domain.
Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain
Neuromorphic engineering (NE) encompasses a diverse range of approaches to information processing that are inspired by neurobiological systems, and this feature distinguishes neuromorphic systems from conventional computing systems.
An FPGA-based Massively Parallel Neuromorphic Cortex Simulator
This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas of the cortex.
A Stochastic Approach to STDP
The decay generator will then generate an exponential decay, which will be used by the STDP adaptor to perform the weight adaption.
A compact aVLSI conductance-based silicon neuron
We present an analogue Very Large Scale Integration (aVLSI) implementation that uses first-order lowpass filters to implement a conductance-based silicon neuron for high-speed neuromorphic systems.
A Reconfigurable Mixed-signal Implementation of a Neuromorphic ADC
The architecture consists of an analogue chip and a control module.
A neuromorphic hardware architecture using the Neural Engineering Framework for pattern recognition
The architecture is not limited to handwriting recognition, but is generally applicable as an extremely fast pattern recognition processor for various kinds of patterns such as speech and images.
A Trainable Neuromorphic Integrated Circuit that Exploits Device Mismatch
Additionally, we characterise each neuron and discuss the statistical variability of its tuning curve that arises due to random device mismatch, a desirable property for the learning capability of the TAB.
An Online Learning Algorithm for Neuromorphic Hardware Implementation
We propose a sign-based online learning (SOL) algorithm for a neuromorphic hardware framework called Trainable Analogue Block (TAB).
A neuromorphic hardware framework based on population coding
These neuronal populations are characterised by a diverse distribution of tuning curves, ensuring that the entire range of input stimuli is encoded.
FPGA Implementation of the CAR Model of the Cochlea
Here, we implement the Cascade of Asymmetric Resonators (CAR) model of the cochlea on an FPGA.
