MATADOR: Automated System-on-Chip Tsetlin Machine Design Generation for Edge Applications

no code implementations • 3 Mar 2024 • Tousif Rahman, Gang Mao, Sidharth Maheshwari, Rishad Shafik, Alex Yakovlev

System-on-Chip Field-Programmable Gate Arrays (SoC-FPGAs) offer significant throughput gains for machine learning (ML) edge inference applications via the design of co-processor accelerator systems.

An FPGA Architecture for Online Learning using the Tsetlin Machine

no code implementations • 1 Jun 2023 • Samuel Prescott, Adrian Wheeldon, Rishad Shafik, Tousif Rahman, Alex Yakovlev, Ole-Christoffer Granmo

We present use cases for online learning using the proposed infrastructure and demonstrate the energy/performance/accuracy trade-offs.

IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines

no code implementations • 22 May 2023 • Omar Ghazal, Simranjeet Singh, Tousif Rahman, Shengqi Yu, Yujin Zheng, Domenico Balsamo, Sachin Patkar, Farhad Merchant, Fei Xia, Alex Yakovlev, Rishad Shafik

Non-volatile memory devices such as Resistive RAM (ReRAM) offer integrated switching and storage capabilities showing promising performance for ML applications.

Energy-frugal and Interpretable AI Hardware Design using Learning Automata

no code implementations • 19 May 2023 • Rishad Shafik, Tousif Rahman, Adrian Wheeldon, Ole-Christoffer Granmo, Alex Yakovlev

Our analyses provides the first insights into conflicting design tradeoffs involved in energy-efficient and interpretable decision models for this new artificial intelligence hardware architecture.