Search Results for author:
Found 13 papers, 9 papers with code
Full Stack Optimization of Transformer Inference: a Survey
In this work, we survey different approaches for efficient Transformer inference, including: (i) analysis and profiling of the bottlenecks in existing Transformer architectures and their similarities and differences with previous convolutional models; (ii) implications of Transformer architecture on hardware, including the impact of non-linear operations such as Layer Normalization, Softmax, and GELU, as well as linear operations, on hardware design; (iii) approaches for optimizing a fixed Transformer architecture; (iv) challenges in finding the right mapping and scheduling of operations for Transformer models; and (v) approaches for optimizing Transformer models by adapting the architecture using neural architecture search.
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators
Recent advances in Deep Neural Networks (DNNs) have led to active development of specialized DNN accelerators, many of which feature a large number of processing elements laid out spatially, together with a multi-level memory hierarchy and flexible interconnect.
HAO: Hardware-aware neural Architecture Optimization for Efficient Inference
Automatic algorithm-hardware co-design for DNN has shown great success in improving the performance of DNNs on FPGAs.
Hardware Aware Neural Architecture Search
Image Classification
+2
HAWQV3: Dyadic Neural Network Quantization
Current low-precision quantization algorithms often have the hidden cost of conversion back and forth from floating point to quantized integer values.
CoDeNet: Efficient Deployment of Input-Adaptive Object Detection on Embedded FPGAs
Deploying deep learning models on embedded systems has been challenging due to limited computing resources.
ProTuner: Tuning Programs with Monte Carlo Tree Search
We explore applying the Monte Carlo Tree Search (MCTS) algorithm in a notoriously difficult task: tuning programs for high-performance deep learning and image processing.
AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning
We compare the performance of AutoPhase to state-of-the-art algorithms that address the phase-ordering problem.
Algorithm-hardware Co-design for Deformable Convolution
In this work, we first investigate the overhead of the deformable convolution on embedded FPGA SoCs, and then show the accuracy-latency tradeoffs for a set of algorithm modifications including full versus depthwise, fixed-shape, and limited-range.
AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs
Domain specialization under energy constraints in deeply-scaled CMOS has been driving the need for agile development of Systems on a Chip (SoCs).
Signal Processing
Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim
We then evaluate the performance of NVDLA by running YOLOv3 object-detection algorithm.
AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning
We implement a framework in the context of the LLVM compiler to optimize the ordering for HLS programs and compare the performance of deep reinforcement learning to state-of-the-art algorithms that address the phase-ordering problem.
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
DiracDeltaNet achieves competitive accuracy on ImageNet (88. 7\% top-5), but with 42$\times$ fewer parameters and 48$\times$ fewer OPs than VGG16.
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud
We present FireSim, an open-source simulation platform that enables cycle-exact microarchitectural simulation of large scale-out clusters by combining FPGA-accelerated simulation of silicon-proven RTL designs with a scalable, distributed network simulation.
