Search Results for author:
Found 13 papers, 3 papers with code
A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog In-Memory Computing
Analog In-Memory Computing (AIMC) is an emerging technology for fast and energy-efficient Deep Learning (DL) inference.
Using the IBM Analog In-Memory Hardware Acceleration Kit for Neural Network Training and Inference
In this tutorial, we provide a deep dive into how such adaptations can be achieved and evaluated using the recently released IBM Analog Hardware Acceleration Kit (AIHWKit), freely available at https://github. com/IBM/aihwkit.
AnalogNAS: A Neural Network Design Framework for Accurate Inference with Analog In-Memory Computing
Digital processors based on typical von Neumann architectures are not conducive to edge AI given the large amounts of required data movement in and out of memory.
Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators
Analog in-memory computing (AIMC) -- a promising approach for energy-efficient acceleration of deep learning workloads -- computes matrix-vector multiplications (MVMs) but only approximately, due to nonidealities that often are non-deterministic or nonlinear.
AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Accelerator
We also describe AON-CiM, a programmable, minimal-area phase-change memory (PCM) analog CiM accelerator, with a novel layer-serial approach to remove the cost of complex interconnects associated with a fully-pipelined design.
A flexible and fast PyTorch toolkit for simulating training and inference on analog crossbar arrays
We introduce the IBM Analog Hardware Acceleration Kit, a new and first of a kind open source toolkit to simulate analog crossbar arrays in a convenient fashion from within PyTorch (freely available at https://github. com/IBM/aihwkit).
Robust High-dimensional Memory-augmented Neural Networks
Traditional neural networks require enormous amounts of data to build their complex mappings during a slow training procedure that hinders their abilities for relearning and adapting to new data.
Few-Shot Image Classification
Vocal Bursts Intensity Prediction
ESSOP: Efficient and Scalable Stochastic Outer Product Architecture for Deep Learning
Strategies to improve the efficiency of MVM computation in hardware have been demonstrated with minimal impact on training accuracy.
Accurate deep neural network inference using computational phase-change memory
In-memory computing is a promising non-von Neumann approach where certain computational tasks are performed within memory units by exploiting the physical attributes of memory devices.
Emerging Technologies
In-memory hyperdimensional computing
Hyperdimensional computing (HDC) is an emerging computational framework that takes inspiration from attributes of neuronal circuits such as hyperdimensionality, fully distributed holographic representation, and (pseudo)randomness.
Supervised Learning in Spiking Neural Networks with Phase-Change Memory Synapses
Combining the computational potential of supervised SNNs with the parallel compute power of computational memory, the work paves the way for next-generation of efficient brain-inspired systems.
Fatiguing STDP: Learning from Spike-Timing Codes in the Presence of Rate Codes
However, some spike-timing-related strengths of SNNs are hindered by the sensitivity of spike-timing-dependent plasticity (STDP) rules to input spike rates, as fine temporal correlations may be obstructed by coarser correlations between firing rates.
Mixed-Precision In-Memory Computing
As CMOS scaling reaches its technological limits, a radical departure from traditional von Neumann systems, which involve separate processing and memory units, is needed in order to significantly extend the performance of today's computers.
Emerging Technologies
