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Found 153 papers, 57 papers with code
Multi-resolution Rescored ByteTrack for Video Object Detection on Ultra-low-power Embedded Systems
This paper introduces Multi-Resolution Rescored Byte-Track (MR2-ByteTrack), a novel video object detection framework for ultra-low-power embedded processors.
Foundation Models for Structural Health Monitoring
For AD, we achieve a near-perfect 99. 9% accuracy with a monitoring time span of just 15 windows.
Optimizing the Deployment of Tiny Transformers on Low-Power MCUs
Moreover, we show that our MHSA depth-first tiling scheme reduces the memory peak by up to 6. 19x, while the fused-weight attention can reduce the runtime by 1. 53x, and number of parameters by 25%.
12 mJ per Class On-Device Online Few-Shot Class-Incremental Learning
In this work, we introduce Online Few-Shot Class-Incremental Learning (O-FSCIL), based on a lightweight model consisting of a pretrained and metalearned feature extractor and an expandable explicit memory storing the class prototypes.
Boosting keyword spotting through on-device learnable user speech characteristics
Keyword spotting systems for always-on TinyML-constrained applications require on-site tuning to boost the accuracy of offline trained classifiers when deployed in unseen inference conditions.
On-Device Domain Learning for Keyword Spotting on Low-Power Extreme Edge Embedded Systems
Keyword spotting accuracy degrades when neural networks are exposed to noisy environments.
SzCORE: A Seizure Community Open-source Research Evaluation framework for the validation of EEG-based automated seizure detection algorithms
Based on existing guidelines and recommendations, the framework introduces a set of recommendations and standards related to datasets, file formats, EEG data input content, seizure annotation input and output, cross-validation strategies, and performance metrics.
A Noisy Beat is Worth 16 Words: a Tiny Transformer for Low-Power Arrhythmia Classification on Microcontrollers
Wearable systems for the long-term monitoring of cardiovascular diseases are becoming widespread and valuable assets in diagnosis and therapy.
A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog In-Memory Computing
Analog In-Memory Computing (AIMC) is an emerging technology for fast and energy-efficient Deep Learning (DL) inference.
Zero-shot Classification using Hyperdimensional Computing
Classification based on Zero-shot Learning (ZSL) is the ability of a model to classify inputs into novel classes on which the model has not previously seen any training examples.
Ranked #3 on
Zero-Shot Learning
on CUB-200-2011
A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation
To the best of the authors' knowledge, it is the first silicon prototype of a ULP SoC coupling the RV64 and RV32 cores in a heterogeneous host+accelerator architecture fully based on the RISC-V ISA.
TCNCA: Temporal Convolution Network with Chunked Attention for Scalable Sequence Processing
We build upon their approach by replacing the linear recurrence with a special temporal convolutional network which permits larger receptive field size with shallower networks, and reduces the computational complexity to $O(L)$.
MIMONets: Multiple-Input-Multiple-Output Neural Networks Exploiting Computation in Superposition
MIMONets augment various deep neural network architectures with variable binding mechanisms to represent an arbitrary number of inputs in a compositional data structure via fixed-width distributed representations.
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures
This survey provides a holistic review of the most influential design methodologies and EDA tools proposed in recent years to implement Deep Learning accelerators, offering the reader a wide perspective in this rapidly evolving field.
Stella Nera: Achieving 161 TOp/s/W with Multiplier-free DNN Acceleration based on Approximate Matrix Multiplication
From classical HPC to deep learning, MatMul is at the heart of today's computing.
Quantitative Evaluation of a Multi-Modal Camera Setup for Fusing Event Data with RGB Images
This work quantitatively evaluates a multi-modal camera setup for fusing high-resolution DVS data with RGB image data by static camera alignment.
Ultra-Efficient On-Device Object Detection on AI-Integrated Smart Glasses with TinyissimoYOLO
To this goal, we designed a smart glasses prototype as a research platform featuring two microcontrollers, including a novel milliwatt-power RISC-V parallel processor with a hardware accelerator for visual AI, and a Bluetooth low-power module for communication.
Ranked #1 on
Object Detection
on PASCAL VOC
Enhancing Neural Architecture Search with Multiple Hardware Constraints for Deep Learning Model Deployment on Tiny IoT Devices
The rapid proliferation of computing domains relying on Internet of Things (IoT) devices has created a pressing need for efficient and accurate deep-learning (DL) models that can run on low-power devices.
Skilog: A Smart Sensor System for Performance Analysis and Biofeedback in Ski Jumping
In particular, a fine-grained control of the center of gravity in the in-run is essential.
Enhancing Performance, Calibration Time and Efficiency in Brain-Machine Interfaces through Transfer Learning and Wearable EEG Technology
The comfortable BMI setup with tiny CNN and TL paves the way to future on-device continual learning, essential for tackling inter-session variability and improving usability.
A Wearable Ultra-Low-Power sEMG-Triggered Ultrasound System for Long-Term Muscle Activity Monitoring
Assuming a muscle contraction of 200 ms at a contraction rate of 1 Hz, the proposed approach enables more than 59% energy saving (with a full-system average power consumption of 12. 2 mW) as compared to operating both sEMG and US continuously.
EpiDeNet: An Energy-Efficient Approach to Seizure Detection for Embedded Systems
The EpiDeNet-SSWCE method demonstrates effective and accurate seizure detection performance on heavily imbalanced datasets, while being suited for implementation on energy-constrained platforms.
Flexible and Fully Quantized Ultra-Lightweight TinyissimoYOLO for Ultra-Low-Power Edge Systems
With this paper, we demonstrate the suitability and flexibility of TinyissimoYOLO on state-of-the-art detection datasets for real-time ultra-low-power edge inference.
ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized Transformers
Transformer networks have emerged as the state-of-the-art approach for natural language processing tasks and are gaining popularity in other domains such as computer vision and audio processing.
Free Bits: Latency Optimization of Mixed-Precision Quantized Neural Networks on the Edge
Mixed-precision quantization, where a deep neural network's layers are quantized to different precisions, offers the opportunity to optimize the trade-offs between model size, latency, and statistical accuracy beyond what can be achieved with homogeneous-bit-width quantization.
BioGAP: a 10-Core FP-capable Ultra-Low Power IoT Processor, with Medical-Grade AFE and BLE Connectivity for Wearable Biosignal Processing
Wearable biosignal processing applications are driving significant progress toward miniaturized, energy-efficient Internet-of-Things solutions for both clinical and consumer applications.
A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms
Recent trends in deep learning (DL) imposed hardware accelerators as the most viable solution for several classes of high-performance computing (HPC) applications such as image classification, computer vision, and speech recognition.
Energy-efficient Wearable-to-Mobile Offload of ML Inference for PPG-based Heart-Rate Estimation
In this work, we propose a collaborative inference approach that uses both a smartwatch and a connected smartphone to maximize the performance of heart rate (HR) tracking while also maximizing the smartwatch's battery life.
Precision-aware Latency and Energy Balancing on Multi-Accelerator Platforms for DNN Inference
The need to execute Deep Neural Networks (DNNs) at low latency and low power at the edge has spurred the development of new heterogeneous Systems-on-Chips (SoCs) encapsulating a diverse set of hardware accelerators.
Reduced Precision Floating-Point Optimization for Deep Neural Network On-Device Learning on MicroControllers
Enabling On-Device Learning (ODL) for Ultra-Low-Power Micro-Controller Units (MCUs) is a key step for post-deployment adaptation and fine-tuning of Deep Neural Network (DNN) models in future TinyML applications.
ColibriUAV: An Ultra-Fast, Energy-Efficient Neuromorphic Edge Processing UAV-Platform with Event-Based and Frame-Based Cameras
The interest in dynamic vision sensor (DVS)-powered unmanned aerial vehicles (UAV) is raising, especially due to the microsecond-level reaction time of the bio-inspired event sensor, which increases robustness and reduces latency of the perception tasks compared to a RGB camera.
Parallelizing Optical Flow Estimation on an Ultra-Low Power RISC-V Cluster for Nano-UAV Navigation
On micro and nano UAVs, real-time calculation of the optical flow is run on low power and resource-constrained microcontroller units (MCUs).
A Fast and Accurate Optical Flow Camera for Resource-Constrained Edge Applications
The paper characterizes the optical flow sensor in high frame-rate, low-latency settings, with a frame rate of up to 88 fps at the full resolution of 1124 by 1364 pixels and up to 240 fps at a reduced camera resolution of 280 by 336, for both classical camera images and optical flow data.
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing
We present Marsellus, an all-digital heterogeneous SoC for AI-IoT end-nodes fabricated in GlobalFoundries 22nm FDX that combines 1) a general-purpose cluster of 16 RISC-V Digital Signal Processing (DSP) cores attuned for the execution of a diverse range of workloads exploiting 4-bit and 2-bit arithmetic extensions (XpulpNN), combined with fused MAC&LOAD operations and floating-point support; 2) a 2-8bit Reconfigurable Binary Engine (RBE) to accelerate 3x3 and 1x1 (pointwise) convolutions in DNNs; 3) a set of On-Chip Monitoring (OCM) blocks connected to an Adaptive Body Biasing (ABB) generator and a hardware control loop, enabling on-the-fly adaptation of transistor threshold voltages.
SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators
To meet the growing need for computational power for DNNs, multiple specialized hardware architectures have been proposed.
Neuromorphic Optical Flow and Real-time Implementation with Event Cameras
Optical flow provides information on relative motion that is an important component in many computer vision pipelines.
Factorizers for Distributed Sparse Block Codes
We provide a methodology to flexibly integrate our factorizer in the classification layer of CNNs with a novel loss function.
Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space
To mitigate the overheads of traditional radiation hardening and modular redundancy approaches, we present a novel Hybrid Modular Redundancy (HMR) approach, a redundancy scheme that features a cluster of RISC-V processors with a flexible on-demand dual-core and triple-core lockstep grouping of computing cores with runtime split-lock capabilities.
Deep Neural Network Architecture Search for Accurate Visual Pose Estimation aboard Nano-UAVs
In this work, we leverage a novel neural architecture search (NAS) technique to automatically identify several Pareto-optimal convolutional neural networks (CNNs) for a visual pose estimation task.
Experimenting with Emerging RISC-V Systems for Decentralised Machine Learning
Federated Learning (FL) and Edge Inference are examples of DML.
Lightweight Neural Architecture Search for Temporal Convolutional Networks at the Edge
Neural Architecture Search (NAS) is quickly becoming the go-to approach to optimize the structure of Deep Learning (DL) models for complex tasks such as Image Classification or Object Detection.
RedMule: A Mixed-Precision Matrix-Matrix Operation Engine for Flexible and Energy-Efficient On-Chip Linear Algebra and TinyML Training Acceleration
The increasing interest in TinyML, i. e., near-sensor machine learning on power budgets of a few tens of mW, is currently pushing toward enabling TinyML-class training as opposed to inference only.
Self-sustaining Ultra-wideband Positioning System for Event-driven Indoor Localization
The energy consumption for position updates, with an accuracy of $40~cm$ (2D) in realistic non-line-of-sight conditions, is $10. 84~mJ$.
Fully On-board Low-Power Localization with Multizone Time-of-Flight Sensors on Nano-UAVs
Experimental evaluation using a nano-UAV open platform demonstrated that the proposed solution is capable of localizing on a 31. 2m$\boldsymbol{^2}$ map with 0. 15m accuracy and an above 95% success rate.
In-memory factorization of holographic perceptual representations
Disentanglement of constituent factors of a sensory signal is central to perception and cognition and hence is a critical task for future artificial intelligence systems.
An Energy-Efficient Spiking Neural Network for Finger Velocity Decoding for Implantable Brain-Machine Interface
Brain-machine interfaces (BMIs) are promising for motor rehabilitation and mobility augmentation.
RUAD: unsupervised anomaly detection in HPC systems
However, current state-of-the-art (SoA) approaches to anomaly detection are supervised and semi-supervised, so they require a human-labelled dataset with anomalies - this is often impractical to collect in production HPC systems.
In-memory Realization of In-situ Few-shot Continual Learning with a Dynamically Evolving Explicit Memory
We demonstrate for the first time how the EM unit can physically superpose multiple training examples, expand to accommodate unseen classes, and perform similarity search during inference, using operations on an IMC core based on phase-change memory (PCM).
Channel-wise Mixed-precision Assignment for DNN Inference on Constrained Edge Nodes
Quantization is widely employed in both cloud and edge systems to reduce the memory occupation, latency, and energy consumption of deep neural networks.
Towards On-device Domain Adaptation for Noise-Robust Keyword Spotting
The accuracy of a keyword spotting model deployed on embedded devices often degrades when the system is exposed to real environments with significant noise.
Multi-Complexity-Loss DNAS for Energy-Efficient and Memory-Constrained Deep Neural Networks
When deployed on a commercial edge device, the STM NUCLEO-H743ZI2, our networks span a range of 2. 18x in energy consumption and 4. 04% in accuracy for the same memory constraint, and reduce energy by up to 2. 2x with negligible accuracy drop with respect to the baseline.
Adaptive Random Forests for Energy-Efficient Inference on Microcontrollers
The accuracy of a RF often increases with the number of internal weak learners (decision trees), but at the cost of a proportional increase in inference latency and energy consumption.
Aerosense: A Self-Sustainable And Long-Range Bluetooth Wireless Sensor Node for Aerodynamic and Aeroacoustic Monitoring on Wind Turbines
This paper presents a low-power, self-sustainable, and modular wireless sensor node for aerodynamic and acoustic measurements on wind turbines and other industrial structures.
Reducing Neural Architecture Search Spaces with Training-Free Statistics and Computational Graph Clustering
The computational demands of neural architecture search (NAS) algorithms are usually directly proportional to the size of their target search spaces.
Energy-Efficient Tree-Based EEG Artifact Detection
In this work we present the implementation of an artifact detection algorithm based on a minimal number of EEG channels on a parallel ultra-low-power (PULP) embedded platform.
Energy-Efficient Adaptive Machine Learning on IoT End-Nodes With Class-Dependent Confidence
Energy-efficient machine learning models that can run directly on edge devices are of great interest in IoT applications, as they can reduce network pressure and response latency, and improve privacy.
Constrained Few-shot Class-incremental Learning
Moreover, it is imperative that such learning must respect certain memory and computational constraints such as (i) training samples are limited to only a few per class, (ii) the computational cost of learning a novel class remains constant, and (iii) the memory footprint of the model grows at most linearly with the number of classes observed.
Ranked #4 on
Few-Shot Class-Incremental Learning
on mini-Imagenet
continual few-shot learning
Few-Shot Class-Incremental Learning
+1
Pruning In Time (PIT): A Lightweight Network Architecture Optimizer for Temporal Convolutional Networks
Temporal Convolutional Networks (TCNs) are promising Deep Learning models for time-series processing tasks.
Robust and Energy-efficient PPG-based Heart-Rate Monitoring
A wrist-worn PPG sensor coupled with a lightweight algorithm can run on a MCU to enable non-invasive and comfortable monitoring, but ensuring robust PPG-based heart-rate monitoring in the presence of motion artifacts is still an open challenge.
MI-BMInet: An Efficient Convolutional Neural Network for Motor Imagery Brain--Machine Interfaces with EEG Channel Selection
A brain--machine interface (BMI) based on motor imagery (MI) enables the control of devices using brain signals while the subject imagines performing a movement.
TCN Mapping Optimization for Ultra-Low Power Time-Series Edge Inference
Temporal Convolutional Networks (TCNs) are emerging lightweight Deep Learning models for Time Series analysis.
Bioformers: Embedding Transformers for Ultra-Low Power sEMG-based Gesture Recognition
Human-machine interaction is gaining traction in rehabilitation tasks, such as controlling prosthetic hands or robotic arms.
Q-PPG: Energy-Efficient PPG-based Heart Rate Monitoring on Wearable Devices
Our most accurate quantized network achieves 4. 41 Beats Per Minute (BPM) of Mean Absolute Error (MAE), with an energy consumption of 47. 65 mJ and a memory footprint of 412 kB.
Training Quantised Neural Networks with STE Variants: the Additive Noise Annealing Algorithm
When testing ANA on the CIFAR-10 image classification benchmark, we find that the major impact on task accuracy is not due to the qualitative shape of the regularisations but to the proper synchronisation of the different STE variants used in a network, in accordance with the theoretical results.
A Neuro-vector-symbolic Architecture for Solving Raven's Progressive Matrices
Compared to state-of-the-art deep neural network and neuro-symbolic approaches, end-to-end training of NVSA achieves a new record of 87. 7% average accuracy in RAVEN, and 88. 1% in I-RAVEN datasets.
Exploring Scalable, Distributed Real-Time Anomaly Detection for Bridge Health Monitoring
Modern real-time Structural Health Monitoring systems can generate a considerable amount of information that must be processed and evaluated for detecting early anomalies and generating prompt warnings and alarms about the civil infrastructure conditions.
Embedding Temporal Convolutional Networks for Energy-Efficient PPG-Based Heart Rate Monitoring
Photoplethysmography (PPG) sensors allow for non-invasive and comfortable heart-rate (HR) monitoring, suitable for compact wrist-worn devices.
Vau da muntanialas: Energy-efficient multi-die scalable acceleration of RNN inference
For quantifying the overall system power, including I/O power, we built Vau da Muntanialas, to the best of our knowledge, the first demonstration of a systolic multi-chip-on-PCB array of RNN accelerator.
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors
The last few years have seen the emergence of IoT processors: ultra-low power systems-on-chips (SoCs) combining lightweight and flexible micro-controller units (MCUs), often based on open-ISA RISC-V cores, with application-specific accelerators to maximize performance and energy efficiency.
A Heterogeneous In-Memory Computing Cluster For Flexible End-to-End Inference of Real-World Deep Neural Networks
Furthermore, we explore the requirements for end-to-end inference of a full mobile-grade DNN (MobileNetV2) in terms of IMC array resources, by scaling up our heterogeneous architecture to a multi-array accelerator.
Sub-100uW Multispectral Riemannian Classification for EEG-based Brain--Machine Interfaces
Motor imagery brain--machine interfaces enable us to control machines by merely thinking of performing a motor action.
A TinyML Platform for On-Device Continual Learning with Quantized Latent Replays
In this work, we introduce a HW/SW platform for end-to-end CL based on a 10-core FP32-enabled parallel ultra-low-power (PULP) processor.
Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode
Vega achieves SoA-leading efficiency of 615 GOPS/W on 8-bit INT computation (boosted to 1. 3TOPS/W for 8-bit DNN inference with hardware acceleration).
Practical Adversarial Attacks on Brain--Computer Interfaces
We propose new methods to induce denial-of-service attacks and incorporate domain-specific insights and constraints to accomplish two key goals: (i) create smooth adversarial attacks that are physiologically plausible; (ii) consider the realistic case where the attack happens at the origin of the signal acquisition and it propagates on the human head.
A Fully-Integrated 5mW, 0.8Gbps Energy-Efficient Chip-to-Chip Data Link for Ultra-Low-Power IoT End-Nodes in 65-nm CMOS
The increasing complexity of Internet-of-Things (IoT) applications and near-sensor processing algorithms is pushing the computational power of low-power, battery-operated end-node systems.
Memory-Aware Partitioning of Machine Learning Applications for Optimal Energy Use in Batteryless Systems
By leveraging interkernel data dependencies, these energy-bounded execution cycles minimize the number of system activations and nonvolatile data transfers, and thus the total energy overhead.
A Construction Kit for Efficient Low Power Neural Network Accelerator Designs
This work provides a survey of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance.
NN2CAM: Automated Neural Network Mapping for Multi-Precision Edge Processing on FPGA-Based Cameras
The record-breaking achievements of deep neural networks (DNNs) in image classification and detection tasks resulted in a surge of new computer vision applications during the past years.
Towards Long-term Non-invasive Monitoring for Epilepsy via Wearable EEG Devices
We present the implementation of seizure detection algorithms based on a minimal number of EEG channels on a parallel ultra-low-power embedded platform.
Trimming Feature Extraction and Inference for MCU-based Edge NILM: a Systematic Approach
State-of-the-Art approaches are based on Machine Learning methods and exploit the fusion of time- and frequency-domain features from current and voltage sensors.
Implementing CNN Layers on the Manticore Cluster-Based Many-Core Architecture
This document presents implementations of fundamental convolutional neural network (CNN) layers on the Manticore cluster-based many-core architecture and discusses their characteristics and trade-offs.
Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Co-design
Artificial intelligence (AI) technologies have dramatically advanced in recent years, resulting in revolutionary changes in people's lives.
ECG-TCN: Wearable Cardiac Arrhythmia Detection with a Temporal Convolutional Network
With 9. 91 GMAC/s/W, it is 23. 0 times more energy-efficient and 46. 85 times faster than an implementation on the ARM Cortex M4F (0. 43 GMAC/s/W).
Mixed-Precision Quantization and Parallel Implementation of Multispectral Riemannian Classification for Brain--Machine Interfaces
With Motor-Imagery (MI) Brain--Machine Interfaces (BMIs) we may control machines by merely thinking of performing a motor action.
A 5 μW Standard Cell Memory-based Configurable Hyperdimensional Computing Accelerator for Always-on Smart Sensing
Hyperdimensional computing (HDC) is a brain-inspired computing paradigm based on high-dimensional holistic representations of vectors.
Sound Event Detection with Binary Neural Networks on Tightly Power-Constrained IoT Devices
This BNN reaches a 77. 9% accuracy, just 7% lower than the full-precision version, with 58 kB (7. 2 times less) for the weights and 262 kB (2. 4 times less) memory in total.
CUTIE: Beyond PetaOp/s/W Ternary DNN Inference Acceleration with Better-than-Binary Energy Efficiency
We present a 3. 1 POp/s/W fully digital hardware accelerator for ternary neural networks.
Hardware Architecture
Binarization Methods for Motor-Imagery Brain-Computer Interface Classification
Our first method, based on sparse bipolar random projection, projects a large number of real-valued Riemannian covariance features to a binary space, where a linear SVM classifier can be learned with binary weights too.
Robust High-dimensional Memory-augmented Neural Networks
Traditional neural networks require enormous amounts of data to build their complex mappings during a slow training procedure that hinders their abilities for relearning and adapting to new data.
Few-Shot Image Classification
Vocal Bursts Intensity Prediction
Leveraging Automated Mixed-Low-Precision Quantization for tiny edge microcontrollers
The severe on-chip memory limitations are currently preventing the deployment of the most accurate Deep Neural Network (DNN) models on tiny MicroController Units (MCUs), even if leveraging an effective 8-bit quantization scheme.
Improving Memory Utilization in Convolutional Neural Network Accelerators
While the accuracy of convolutional neural networks has achieved vast improvements by introducing larger and deeper network architectures, also the memory footprint for storing their parameters and activations has increased.
Always-On 674uW @ 4GOP/s Error Resilient Binary Neural Networks with Aggressive SRAM Voltage Scaling on a 22nm IoT End-Node
On a prototype in 22nm FDX technology, we demonstrate that both the logic and SRAM voltage can be dropped to 0. 5Vwithout any accuracy penalty on a BNN trained for the CIFAR-10 dataset, improving energy efficiency by 2. 2X w. r. t.
A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22$\%$ INL
Clock generators are an essential and critical building block of any communication link, whether it be wired or wireless, and they are increasingly critical given the push for lower I/O power and higher bandwidth in Systems-on-Chip (SoCs) for the Internet-of-Things (IoT).
TinyRadarNN: Combining Spatial and Temporal Convolutional Neural Networks for Embedded Gesture Recognition with Short Range Radars
Furthermore, the gesture recognition classifier has been implemented on a Parallel Ultra-Low Power Processor, demonstrating that real-time prediction is feasible with only 21 mW of power consumption for the full TCN sequence prediction network, while a system-level power consumption of less than 100 mW is achieved.
Automated Design Space Exploration for optimised Deployment of DNN on Arm Cortex-A CPUs
The framework relies on a Reinforcement Learning search that, combined with a deep learning inference framework, automatically explores the design space and learns an optimised solution that speeds up the performance and reduces the memory on embedded CPU platforms.
EEG-TCNet: An Accurate Temporal Convolutional Network for Embedded Motor-Imagery Brain-Machine Interfaces
Experimental results on the BCI Competition IV-2a dataset show that EEG-TCNet achieves 77. 35% classification accuracy in 4-class MI.
ChewBaccaNN: A Flexible 223 TOPS/W BNN Accelerator
Furthermore, it can perform inference on a binarized ResNet-18 trained with 8-bases Group-Net to achieve a 67. 5% Top-1 accuracy with only 3. 0 mJ/frame -- at an accuracy drop of merely 1. 8% from the full-precision ResNet-18.
Optimizing Temporal Convolutional Network inference on FPGA-based accelerators
Convolutional Neural Networks are extensively used in a wide range of applications, commonly including computer vision tasks like image and video classification, recognition, and segmentation.
Q-EEGNet: an Energy-Efficient 8-bit Quantized Parallel EEGNet Implementation for Edge Motor-Imagery Brain--Machine Interfaces
We quantize weights and activations to 8-bit fixed-point with a negligible accuracy loss of 0. 4% on 4-class MI, and present an energy-efficient hardware-aware implementation on the Mr. Wolf parallel ultra-low power (PULP) System-on-Chip (SoC) by utilizing its custom RISC-V ISA extensions and 8-core compute cluster.
LLHD: A Multi-level Intermediate Representation for Hardware Description Languages
These tools are monolithic and mostly proprietary, disagree in their implementation of HDLs, and while many redundant IRs exists, no IR today can be used through the entire circuit design flow.
Programming Languages
pAElla: Edge-AI based Real-Time Malware Detection in Data Centers
The method -- called pAElla -- targets real-time Malware Detection (MD), it runs on an out-of-band IoT-based monitoring system for DCs/SCs, and involves Power Spectral Density of power measurements, along with AutoEncoders.
An Accurate EEGNet-based Motor-Imagery Brain-Computer Interface for Low-Power Edge Computing
Our novel method further scales down the standard EEGNet at a negligible accuracy loss of 0. 31% with 7. 6x memory footprint reduction and a small accuracy loss of 2. 51% with 15x reduction.
InfiniWolf: Energy Efficient Smart Bracelet for Edge Computing with Dual Source Energy Harvesting
This work presents InfiniWolf, a novel multi-sensor smartwatch that can achieve self-sustainability exploiting thermal and solar energy harvesting, performing computationally high demanding tasks.
Extending the RISC-V ISA for Efficient RNN-based 5G Radio Resource Management
Radio Resource Management (RRM) in 5G mobile communication is a challenging problem for which Recurrent Neural Networks (RNN) have shown promising results.
Combining Learning and Optimization for Transprecision Computing
The ML model learns the relation between variables precision and the output error; this information is then embedded in the MP focused on minimizing the number of bits.
Distributed, Parallel, and Cluster Computing
RPR: Random Partition Relaxation for Training; Binary and Ternary Weight Neural Networks
We present Random Partition Relaxation (RPR), a method for strong quantization of neural networks weight to binary (+1/-1) and ternary (+1/0/-1) values.
HR-SAR-Net: A Deep Neural Network for Urban Scene Segmentation from High-Resolution SAR Data
Synthetic aperture radar (SAR) data is becoming increasingly available to a wide range of users through commercial service providers with resolutions reaching 0. 5m/px.
Constrained deep neural network architecture search for IoT devices accounting for hardware calibration
The narrow-space search of floating-point models improves the accuracy on CIFAR10 of an established IoT model from 70. 64% to 74. 87% within the same memory constraints.
FANN-on-MCU: An Open-Source Toolkit for Energy-Efficient Neural Network Inference at the Edge of the Internet of Things
The growing number of low-power smart devices in the Internet of Things is coupled with the concept of "Edge Computing", that is moving some of the intelligence, especially machine learning, towards the edge of the network.
Constrained deep neural network architecture search for IoT devices accounting hardware calibration
We further improve the accuracy to 82. 07% by including 16-bit half types and we obtain the best accuracy of 83. 45% by extending the search with model optimized IEEE 754 reduced types.
EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators
In the wake of the success of convolutional neural networks in image classification, object recognition, speech recognition, etc., the demand for deploying these compute-intensive ML models on embedded and mobile systems with tight power and energy constraints at low cost, as well as for boosting throughput in data centers, is growing rapidly.
PULP-NN: Accelerating Quantized Neural Networks on Parallel Ultra-Low-Power RISC-V Processors
We present PULP-NN, an optimized computing library for a parallel ultra-low-power tightly coupled cluster of RISC-V processors.
5 Parallel Prism: A topology for pipelined implementations of convolutional neural networks using computational memory
We show that this communication fabric facilitates the pipelined execution of all state of-the-art CNNs by proving the existence of a homomorphism between one graph representation of these networks and the proposed graph topology.
In-memory hyperdimensional computing
Hyperdimensional computing (HDC) is an emerging computational framework that takes inspiration from attributes of neuronal circuits such as hyperdimensionality, fully distributed holographic representation, and (pseudo)randomness.
Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI
In this paper, we present Ara, a 64-bit vector processor based on the version 0. 5 draft of RISC-V's vector extension, implemented in GlobalFoundries 22FDX FD-SOI technology.
Hardware Architecture
Memory-Driven Mixed Low Precision Quantization For Enabling Deep Network Inference On Microcontrollers
To fit the memory and computational limitations of resource-constrained edge-devices, we exploit mixed low-bitwidth compression, featuring 8, 4 or 2-bit uniform quantization, and we model the inference graph with integer-only operations.
Additive Noise Annealing and Approximation Properties of Quantized Neural Networks
We present a theoretical and experimental investigation of the quantization problem for artificial neural networks.
An Open Source and Open Hardware Deep Learning-powered Visual Navigation Engine for Autonomous Nano-UAVs
Nano-size unmanned aerial vehicles (UAVs), with few centimeters of diameter and sub-10 Watts of total power budget, have so far been considered incapable of running sophisticated visual-based autonomous navigation software without external aid from base-stations, ad-hoc local positioning infrastructure, and powerful external computation servers.
Online Anomaly Detection in HPC Systems
Reliability is a cumbersome problem in High Performance Computing Systems and Data Centers evolution.
Distributed, Parallel, and Cluster Computing
Optimally Scheduling CNN Convolutions for Efficient Memory Access
Embedded inference engines for convolutional networks must be parsimonious in memory bandwidth and buffer sizing to meet power and cost constraints.
Bonseyes AI Pipeline -- bringing AI to you. End-to-end integration of data, algorithms and deployment tools
In this work, we present a modular AI pipeline as an integrating framework to bring data, algorithms, and deployment tools together.
Analysis of Contraction Effort Level in EMG-Based Gesture Recognition Using Hyperdimensional Computing
Varying contraction levels of muscles is a big challenge in electromyography-based gesture recognition.
Exploring Embedding Methods in Binary Hyperdimensional Computing: A Case Study for Motor-Imagery based Brain-Computer Interfaces
All these methods, differing in complexity, aim to represent EEG signals in binary HD space, e. g. with 10, 000 bits.
Learning to infer: RL-based search for DNN primitive selection on Heterogeneous Embedded Systems
In this work, we present QS-DNN, a fully automatic search based on Reinforcement Learning which, combined with an inference engine optimizer, efficiently explores through the design space and empirically finds the optimal combinations of libraries and primitives to speed up the inference of CNNs on heterogeneous embedded devices.
QUENN: QUantization Engine for low-power Neural Networks
Deep Learning is moving to edge devices, ushering in a new age of distributed Artificial Intelligence (AI).
Anomaly Detection using Autoencoders in High Performance Computing Systems
Anomaly detection in supercomputers is a very difficult problem due to the big scale of the systems and the high number of components.
Robust identification of thermal models for in-production High-Performance-Computing clusters with machine learning-based data selection
However, we also show that: 1) not all real workloads allow for the identification of a good model; 2) starting from the theory of system identification it is very difficult to evaluate if a trace of data leads to a good estimated model.
Extended Bit-Plane Compression for Convolutional Neural Network Accelerators
After the tremendous success of convolutional neural networks in image classification, object detection, speech recognition, etc., there is now rising demand for deployment of these compute-intensive ML models on tightly power constrained embedded and mobile systems at low cost as well as for pushing the throughput in data centers.
One-shot Learning for iEEG Seizure Detection Using End-to-end Binary Operations: Local Binary Patterns with Hyperdimensional Computing
This paper presents an efficient binarized algorithm for both learning and classification of human epileptic seizures from intracranial electroencephalography (iEEG).
CBinfer: Exploiting Frame-to-Frame Locality for Faster Convolutional Network Inference on Video Streams
The last few years have brought advances in computer vision at an amazing pace, grounded on new findings in deep neural network construction and training as well as the availability of large labeled datasets.
Hardware Optimizations of Dense Binary Hyperdimensional Computing: Rematerialization of Hypervectors, Binarized Bundling, and Combinational Associative Memory
In this paper, we propose hardware techniques for optimizations of HD computing, in a synthesizable VHDL library, to enable co-located implementation of both learning and classification tasks on only a small portion of Xilinx(R) UltraScale(TM) FPGAs: (1) We propose simple logical operations to rematerialize the hypervectors on the fly rather than loading them from memory.
XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference
Binary Neural Networks (BNNs) are promising to deliver accuracy comparable to conventional deep neural networks at a fraction of the cost in terms of memory and energy.
COUNTDOWN - three, two, one, low power! A Run-time Library for Energy Saving in MPI Communication Primitives
Power consumption is a looming treat in today's computing progress.
Distributed, Parallel, and Cluster Computing
Fast and Accurate Multiclass Inference for MI-BCIs Using Large Multiscale Temporal and Spectral Features
Accurate, fast, and reliable multiclass classification of electroencephalography (EEG) signals is a challenging task towards the development of motor imagery brain-computer interface (MI-BCI) systems.
A 64mW DNN-based Visual Navigation Engine for Autonomous Nano-Drones
As part of our general methodology we discuss the software mapping techniques that enable the state-of-the-art deep convolutional neural network presented in [1] to be fully executed on-board within a strict 6 fps real-time constraint with no compromise in terms of flight results, while all processing is done with only 64 mW on average.
Efficient Image Dataset Classification Difficulty Estimation for Predicting Deep-Learning Accuracy
In the deep-learning community new algorithms are published at an incredible pace.
XNORBIN: A 95 TOp/s/W Hardware Accelerator for Binary Convolutional Neural Networks
Deploying state-of-the-art CNNs requires power-hungry processors and off-chip memory.
Hyperdrive: A Multi-Chip Systolically Scalable Binary-Weight CNN Inference Engine
Deep neural networks have achieved impressive results in computer vision and machine learning.
An EMG Gesture Recognition System with Flexible High-Density Sensors and Brain-Inspired High-Dimensional Classifier
We present an end-to-end system combating this variability using a large-area, high-density sensor array and a robust classification algorithm.
A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets
Most investigations into near-memory hardware accelerators for deep neural networks have primarily focused on inference, while the potential of accelerating training has received relatively little attention so far.
Distributed, Parallel, and Cluster Computing Hardware Architecture
HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA
Heterogeneous embedded systems on chip (HESoCs) co-integrate a standard host processor with programmable manycore accelerators (PMCAs) to combine general-purpose computing with domain-specific, efficient processing capabilities.
Hardware Architecture Distributed, Parallel, and Cluster Computing
NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs
Deep convolutional neural networks (CNNs) obtain outstanding results in tasks that require human-level understanding of data, like image or speech recognition.
Design Automation for Binarized Neural Networks: A Quantum Leap Opportunity?
Design automation in general, and in particular logic synthesis, can play a key role in enabling the design of application-specific Binarized Neural Networks (BNN).
Chipmunk: A Systolically Scalable 0.9 mm${}^2$, 3.08 Gop/s/mW @ 1.2 mW Accelerator for Near-Sensor Recurrent Neural Network Inference
Recurrent neural networks (RNNs) are state-of-the-art in voice awareness/understanding and speech recognition.
CBinfer: Change-Based Inference for Convolutional Neural Networks on Video Data
Extracting per-frame features using convolutional neural networks for real-time processing of video data is currently mainly performed on powerful GPU-accelerated workstations and compute clusters.
Soft-to-Hard Vector Quantization for End-to-End Learning Compressible Representations
We present a new approach to learn compressible representations in deep architectures with an end-to-end training strategy.
Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes
Our codesign approach consists of a network of Smart Memory Cubes (modular extensions to the standard HMC) each augmented with a many-core PIM platform called NeuroCluster.
Hardware Architecture Emerging Technologies
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
Near-sensor data analytics is a promising direction for IoT endpoints, as it minimizes energy spent on communication and reduces network load - but it also poses security concerns, as valuable data is stored or sent over the network at various stages of the analytics pipeline.
CAS-CNN: A Deep Convolutional Neural Network for Image Compression Artifact Suppression
Lossy image compression algorithms are pervasively used to reduce the size of images transmitted over the web and recorded on data storage media.
Computationally Efficient Target Classification in Multispectral Image Data with Deep Neural Networks
The required communication links and archiving of the video data are still expensive and this setup excludes preemptive actions to respond to imminent threats.
Deep Structured Features for Semantic Segmentation
We propose a highly structured neural network architecture for semantic segmentation with an extremely small model size, suitable for low-power embedded and mobile platforms.
YodaNN: An Architecture for Ultra-Low Power Binary-Weight CNN Acceleration
Convolutional neural networks (CNNs) have revolutionized the world of computer vision over the last few years, pushing image classification beyond human accuracy.
Origami: A 803 GOp/s/W Convolutional Network Accelerator
An ever increasing number of computer vision and image/video processing challenges are being approached using deep convolutional neural networks, obtaining state-of-the-art results in object recognition and detection, semantic segmentation, action recognition, optical flow and superresolution.
