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Found 11 papers, 4 papers with code
A Survey on Graph Neural Network Acceleration: Algorithms, Systems, and Customized Hardware
Graph neural networks (GNNs) are emerging for machine learning research on graph-structured data.
ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation
In addition, these programs can be compiled and converted into a control data flow graph (CDFG), and the compiler also provides fine-grained alignment between the code tokens and the CDFG nodes.
FPGA-Based In-Vivo Calcium Image Decoding for Closed-Loop Feedback Applications
Our FPGA implementation enables the real-time calcium image decoding with sub-ms processing latency for closed-loop feedback applications.
Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks
High-level synthesis (HLS) has freed the computer architects from developing their designs in a very low-level language and needing to exactly specify how the data should be transferred in register-level.
SPA-GCN: Efficient and Flexible GCN Accelerator with an Application for Graph Similarity Computation
While there have been many studies on hardware acceleration for deep learning on images, there has been a rather limited focus on accelerating deep learning applications involving graphs.
Pyxis: An Open-Source Performance Dataset of Sparse Accelerators
In this work, we present PYXIS, a performance dataset for specialized accelerators on sparse data.
When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization
With the recent release of High Bandwidth Memory (HBM) based FPGA boards, developers can now exploit unprecedented external memory bandwidth.
Hardware Architecture
SACNN: Self-Attention Convolutional Neural Network for Low-Dose CT Denoising With Self-Supervised Perceptual Loss Network
We combine these two methods and demonstrate their effectiveness on both CNN-based neural networks and WGAN-based neural networks with comprehensive experiments.
Optimality Study of Existing Quantum Computing Layout Synthesis Tools
In this paper, we construct QUEKO benchmarks for this problem, which have known optimal depth.
Quantum Physics Hardware Architecture
AutoAccel: Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture
Such a well-defined template is able to support efficient accelerator designs for a broad class of computation kernels, and more importantly, drastically reduce the design space.
Distributed, Parallel, and Cluster Computing Hardware Architecture
Computed Tomography Image Enhancement using 3D Convolutional Neural Network
Computed tomography (CT) is increasingly being used for cancer screening, such as early detection of lung cancer.
