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Fast System Technology Co-Optimization Framework for Emerging Technology Based on Graph Neural Networks
This paper proposes a fast system technology co-optimization (STCO) framework that optimizes power, performance, and area (PPA) for next-generation IC design, addressing the challenges and opportunities presented by novel materials and device architectures.
Chiplet Placement Order Exploration Based on Learning to Rank with Graph Representation
Chiplet-based systems, integrating various silicon dies manufactured at different integrated circuit technology nodes on a carrier interposer, have garnered significant attention in recent years due to their cost-effectiveness and competitive performance.
Fast Cell Library Characterization for Design Technology Co-Optimization Based on Graph Neural Networks
Our model achieves precise predictions, with absolute error $\le$3. 0 ps for WNS, percentage errors $\le$0. 60% for leakage power, and $\le$0. 99% for dynamic power, when compared to golden reference.
