Search Results for author:
Found 5 papers, 2 papers with code
Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design
By jointly optimizing the algorithm and hardware, our FPGA-based butterfly accelerator achieves 14. 2 to 23. 2 times speedup over state-of-the-art accelerators normalized to the same computational budget.
Zero-Cost Operation Scoring in Differentiable Architecture Search
From this perspective, we introduce a novel \textit{perturbation-based zero-cost operation scoring} (Zero-Cost-PT) approach, which utilizes zero-cost proxies that were recently studied in multi-trial NAS but degrade significantly on larger search spaces, typical for differentiable NAS.
NAS-Bench-ASR: Reproducible Neural Architecture Search for Speech Recognition
These datasets, however, focus predominantly on computer vision and NLP tasks and thus suffer from the problem of limited coverage of application domains.
Automatic Speech Recognition
Automatic Speech Recognition (ASR)
+2
BRP-NAS: Prediction-based NAS using GCNs
What is more, we investigate prediction quality on different metrics and show that sample efficiency of the predictor-based NAS can be improved by considering binary relations of models and an iterative data selection strategy.
Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Accelerator
We automate HW-CNN codesign using NAS by including parameters from both the CNN model and the HW accelerator, and we jointly search for the best model-accelerator pair that boosts accuracy and efficiency.
