Search Results for author: Hongxiang Fan

Found 10 papers, 4 papers with code

SAE: Single Architecture Ensemble Neural Networks

no code implementations9 Feb 2024 Martin Ferianc, Hongxiang Fan, Miguel Rodrigues

Ensembles of separate neural networks (NNs) have shown superior accuracy and confidence calibration over single NN across tasks.

Image Classification

Sparse-DySta: Sparsity-Aware Dynamic and Static Scheduling for Sparse Multi-DNN Workloads

1 code implementation17 Oct 2023 Hongxiang Fan, Stylianos I. Venieris, Alexandros Kouris, Nicholas D. Lane

Running multiple deep neural networks (DNNs) in parallel has become an emerging workload in both edge devices, such as mobile phones where multiple tasks serve a single user for daily activities, and data centers, where various requests are raised from millions of users, as seen with large language models.

Scheduling

When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA

1 code implementation13 Aug 2023 Hongxiang Fan, Hao Chen, Liam Castelli, Zhiqiang Que, He Li, Kenneth Long, Wayne Luk

Bayesian Neural Networks (BayesNNs) have demonstrated their capability of providing calibrated prediction for safety-critical applications such as medical imaging and autonomous driving.

Autonomous Driving

LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics

1 code implementation28 Sep 2022 Zhiqiang Que, Hongxiang Fan, Marcus Loo, He Li, Michaela Blott, Maurizio Pierini, Alexander Tapper, Wayne Luk

This work presents a novel reconfigurable architecture for Low Latency Graph Neural Network (LL-GNN) designs for particle detectors, delivering unprecedented low latency performance.

Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design

no code implementations20 Sep 2022 Hongxiang Fan, Thomas Chau, Stylianos I. Venieris, Royson Lee, Alexandros Kouris, Wayne Luk, Nicholas D. Lane, Mohamed S. Abdelfattah

By jointly optimizing the algorithm and hardware, our FPGA-based butterfly accelerator achieves 14. 2 to 23. 2 times speedup over state-of-the-art accelerators normalized to the same computational budget.

Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator

no code implementations24 Nov 2021 Hongxiang Fan, Martin Ferianc, Zhiqiang Que, He Li, Shuanglong Liu, Xinyu Niu, Wayne Luk

Recent advances in algorithm-hardware co-design for deep neural networks (DNNs) have demonstrated their potential in automatically designing neural architectures and hardware designs.

Optimizing Bayesian Recurrent Neural Networks on an FPGA-based Accelerator

no code implementations4 Jun 2021 Martin Ferianc, Zhiqiang Que, Hongxiang Fan, Wayne Luk, Miguel Rodrigues

To further improve the overall algorithmic-hardware performance, a co-design framework is proposed to explore the most fitting algorithmic-hardware configurations for Bayesian RNNs.

Time Series Analysis

High-Performance FPGA-based Accelerator for Bayesian Neural Networks

no code implementations12 May 2021 Hongxiang Fan, Martin Ferianc, Miguel Rodrigues, HongYu Zhou, Xinyu Niu, Wayne Luk

Neural networks (NNs) have demonstrated their potential in a wide range of applications such as image recognition, decision making or recommendation systems.

Autonomous Vehicles Bayesian Inference +3

ComBiNet: Compact Convolutional Bayesian Neural Network for Image Segmentation

1 code implementation14 Apr 2021 Martin Ferianc, Divyansh Manocha, Hongxiang Fan, Miguel Rodrigues

Fully convolutional U-shaped neural networks have largely been the dominant approach for pixel-wise image segmentation.

Bayesian Inference Decision Making +3

VINNAS: Variational Inference-based Neural Network Architecture Search

no code implementations12 Jul 2020 Martin Ferianc, Hongxiang Fan, Miguel Rodrigues

In recent years, neural architecture search (NAS) has received intensive scientific and industrial interest due to its capability of finding a neural architecture with high accuracy for various artificial intelligence tasks such as image classification or object detection.

Computational Efficiency Image Classification +4

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