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Found 8 papers, 1 papers with code
Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS
Existing large language models (LLMs) for register transfer level code generation face challenges like compilation failures and suboptimal power, performance, and area (PPA) efficiency.
Towards the Imagenets of ML4EDA
Here we describe our experience curating two large-scale, high-quality datasets for Verilog code generation and logic synthesis.
Are Emily and Greg Still More Employable than Lakisha and Jamal? Investigating Algorithmic Hiring Bias in the Era of ChatGPT
We replicate this experiment on state-of-art LLMs (GPT-3. 5, Bard, Claude and Llama) to evaluate bias (or lack thereof) on gender, race, maternity status, pregnancy status, and political affiliation.
VeriGen: A Large Language Model for Verilog Code Generation
In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by generating high-quality Verilog code, a common language for designing and modeling digital systems.
LLM-assisted Generation of Hardware Assertions
As vulnerabilities in hardware can have severe implications on a system, there is a need for techniques to support security verification activities.
Security and Interpretability in Automotive Systems
The lack of any sender authentication mechanism in place makes CAN (Controller Area Network) vulnerable to security threats.
Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Automating hardware design could obviate a significant amount of human error from the engineering process and lead to fewer errors.
A generalizable saliency map-based interpretation of model outcome
To fully exploit the capabilities of complex neural networks, we propose a non-intrusive interpretability technique that uses the input and output of the model to generate a saliency map.
