CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generation

no code implementations • 12 Apr 2024 • Matthew DeLorenzo, Vasudev Gohil, Jeyavijayan Rajendran

Large Language Models (LLMs) have proved effective and efficient in generating code, leading to their utilization within the hardware design process.

Code Generation

Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing

no code implementations • 10 Apr 2024 • Mohamadreza Rostami, Marco Chilese, Shaza Zeitouni, Rahul Kande, Jeyavijayan Rajendran, Ahmad-Reza Sadeghi

ChatFuzz achieves condition coverage rate of 75% in just 52 minutes compared to a state-of-the-art fuzzer, which requires a lengthy 30-hour window to reach a similar condition coverage.

Vulnerability Detection

AttackGNN: Red-Teaming GNNs in Hardware Security Using Reinforcement Learning

no code implementations • 21 Feb 2024 • Vasudev Gohil, Satwik Patnaik, Dileep Kalathil, Jeyavijayan Rajendran

We target five GNN-based techniques for four crucial classes of problems in hardware security: IP piracy, detecting/localizing HTs, reverse engineering, and hardware obfuscation.

reinforcement-learning Reinforcement Learning (RL)

Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS

no code implementations • 5 Feb 2024 • Matthew DeLorenzo, Animesh Basak Chowdhury, Vasudev Gohil, Shailja Thakur, Ramesh Karri, Siddharth Garg, Jeyavijayan Rajendran

Existing large language models (LLMs) for register transfer level code generation face challenges like compilation failures and suboptimal power, performance, and area (PPA) efficiency.

Code Generation Language Modelling

LLM-assisted Generation of Hardware Assertions

no code implementations • 24 Jun 2023 • Rahul Kande, Hammond Pearce, Benjamin Tan, Brendan Dolan-Gavitt, Shailja Thakur, Ramesh Karri, Jeyavijayan Rajendran

As vulnerabilities in hardware can have severe implications on a system, there is a need for techniques to support security verification activities.

Code Generation