2 code implementations • 8 Apr 2024 • Miguel Costa, Sandro Pinto
To fill this gap, we empirically evaluate the effectiveness of attacks and defenses from (full-precision) ANNs on (constrained) QNNs.
no code implementations • 7 Jan 2024 • Luca Valente, Alessandro Nadalini, Asif Veeran, Mattia Sinigaglia, Bruno Sa, Nils Wistoff, Yvan Tortorella, Simone Benatti, Rafail Psiakis, Ari Kulmala, Baker Mohammad, Sandro Pinto, Daniele Palossi, Luca Benini, Davide Rossi
To the best of the authors' knowledge, it is the first silicon prototype of a ULP SoC coupling the RV64 and RV32 cores in a heterogeneous host+accelerator architecture fully based on the RISC-V ISA.
1 code implementation • 6 Oct 2021 • Miguel Costa, Diogo Costa, Tiago Gomes, Sandro Pinto
In terms of throughput, our Arm Cortex-M API enables the execution of primary capsule and capsule layers with medium-sized kernels in just 119. 94 and 90. 60 milliseconds (ms), respectively (STM32H755ZIT6U, Cortex-M7 @ 480 MHz).