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Found 18 papers, 6 papers with code
Learning from Teaching Regularization: Generalizable Correlations Should be Easy to Imitate
The student learners are trained by the main model and improve the main model to capture more generalizable and teachable correlations by providing feedback.
Zero-Space Cost Fault Tolerance for Transformer-based Language Models on ReRAM
Resistive Random Access Memory (ReRAM) has emerged as a promising platform for deep neural networks (DNNs) due to its support for parallel in-situ matrix-vector multiplication.
Medusa: Simple LLM Inference Acceleration Framework with Multiple Decoding Heads
We present two levels of fine-tuning procedures for Medusa to meet the needs of different use cases: Medusa-1: Medusa is directly fine-tuned on top of a frozen backbone LLM, enabling lossless inference acceleration.
MaxK-GNN: Extremely Fast GPU Kernel Design for Accelerating Graph Neural Networks Training
In this paper, we present MaxK-GNN, an advanced high-performance GPU training system integrating algorithm and system innovation.
Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis
The increasing use of Advanced Language Models (ALMs) in diverse sectors, particularly due to their impressive capability to generate top-tier content following linguistic instructions, forms the core of this investigation.
Evaluating Emerging AI/ML Accelerators: IPU, RDU, and NVIDIA/AMD GPUs
The relentless advancement of artificial intelligence (AI) and machine learning (ML) applications necessitates the development of specialized hardware accelerators capable of handling the increasing complexity and computational demands.
Accel-GCN: High-Performance GPU Accelerator Design for Graph Convolution Networks
Utilizing these principles, we formulated a kernel for sparse matrix multiplication (SpMM) in GCNs that employs block-level partitioning and combined warp strategy.
AutoReP: Automatic ReLU Replacement for Fast Private Network Inference
The growth of the Machine-Learning-As-A-Service (MLaaS) market has highlighted clients' data privacy and security issues.
RRNet: Towards ReLU-Reduced Neural Network for Two-party Computation Based Private Inference
The proliferation of deep learning (DL) has led to the emergence of privacy and security concerns.
Dynamic Sparse Training via Balancing the Exploration-Exploitation Trade-off
We further design an acquisition function and provide the theoretical guarantees for the proposed method and clarify its convergence property.
PolyMPCNet: Towards ReLU-free Neural Architecture Search in Two-party Computation Based Private Inference
The rapid growth and deployment of deep learning (DL) has witnessed emerging privacy and security concerns.
Towards Sparsification of Graph Neural Networks
In this paper, we utilize two state-of-the-art model compression methods (1) train and prune and (2) sparse training for the sparsification of weight layers in GNNs.
A Length Adaptive Algorithm-Hardware Co-design of Transformer on FPGA Through Sparse Attention and Dynamic Pipelining
Particularly, we develop a hardware-friendly sparse attention operator and a length-aware hardware resource scheduling algorithm.
An Automatic and Efficient BERT Pruning for Edge AI Systems
On MRPC, we obtain a 4. 6 higher score than the SOTA at the same overall pruning ratio of 0. 5.
Accelerating Framework of Transformer by Hardware Design and Model Compression Co-Optimization
Our HP can achieve higher sparsity ratio and is more flexible than other sparsity pattern.
Detecting Gender Bias in Transformer-based Models: A Case Study on BERT
In this paper, we propose a novel gender bias detection method by utilizing attention map for transformer-based models.
Binary Complex Neural Network Acceleration on FPGA
Deep complex networks (DCN), in contrast, can learn from complex data, but have high computational costs; therefore, they cannot satisfy the instant decision-making requirements of many deployable systems dealing with short observations or short signal bursts.
Improving DNN Fault Tolerance using Weight Pruning and Differential Crossbar Mapping for ReRAM-based Edge AI
More importantly, our method does not require extra hardware cost compared to the traditional two-column mapping scheme.
