Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach

1 code implementation • 18 Jul 2018 • Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu

In spite of maturity to the modern electronic design automation (EDA) tools, optimized designs at architectural stage may become sub-optimal after going through physical design flow.

Active Learning BIG-bench Machine Learning