Search Results for author: Sharad Sinha

Found 9 papers, 0 papers with code

Joint-YODNet: A Light-weight Object Detector for UAVs to Achieve Above 100fps

no code implementations27 Sep 2023 Vipin Gautam, Shitala Prasad, Sharad Sinha

Small object detection via UAV (Unmanned Aerial Vehicle) images captured from drones and radar is a complex task with several formidable challenges.

object-detection Small Object Detection

AaP-ReID: Improved Attention-Aware Person Re-identification

no code implementations27 Sep 2023 Vipin Gautam, Shitala Prasad, Sharad Sinha

Person re-identification (ReID) is a well-known problem in the field of computer vision.

Person Re-Identification

YOLORe-IDNet: An Efficient Multi-Camera System for Person-Tracking

no code implementations23 Sep 2023 Vipin Gautam, Shitala Prasad, Sharad Sinha

Its ability to track targets without prior knowledge or historical data is a significant improvement over existing systems, making it well-suited for public safety and surveillance applications.

Person Re-Identification

Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System

no code implementations11 Dec 2020 Zhe Lin, Sharad Sinha, Wei zhang

Following this, we present Hard-ODT, a high-performance, hardware-efficient and scalable online decision tree learning system on a field-programmable gate array (FPGA) with system-level optimization techniques.

Decision Tree Based Hardware Power Monitoring for Run Time Dynamic Power Management in FPGA

no code implementations3 Sep 2020 Zhe Lin, Wei zhang, Sharad Sinha

A flexible architecture of the hardware power monitoring is proposed, which can be instrumented in any RTL design for runtime power estimation, dispensing with the need for extra power measurement devices.

Management

An Ensemble Learning Approach for In-situ Monitoring of FPGA Dynamic Power

no code implementations3 Sep 2020 Zhe Lin, Sharad Sinha, Wei zhang

As field-programmable gate arrays become prevalent in critical application domains, their power consumption is of high concern.

Ensemble Learning Management

Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA

no code implementations3 Sep 2020 Zhe Lin, Sharad Sinha, Wei zhang

We further present a high-performance, hardware-efficient and scalable online decision tree learning system on a field-programmable gate array (FPGA) with system-level optimization techniques.

FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications

no code implementations5 Jun 2020 Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei zhang, Shaojie Shen

To reduce the design effort and achieve the right balance, we propose FP-Stereo for building high-performance stereo matching pipelines on FPGAs automatically.

C++ code Depth Estimation +1

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis

no code implementations6 May 2019 Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei zhang

Early and accurate congestion estimation is of great benefit to guide the optimization in HLS and improve the efficiency of implementation.

BIG-bench Machine Learning Face Detection +1

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