Search Results for author:
Found 6 papers, 2 papers with code
HW-V2W-Map: Hardware Vulnerability to Weakness Mapping Framework for Root Cause Analysis with GPT-assisted Mitigation Suggestion
The escalating complexity of modern computing frameworks has resulted in a surge in the cybersecurity vulnerabilities reported to the National Vulnerability Database (NVD) by practitioners.
A Neural Network-based SAT-Resilient Obfuscation Towards Enhanced Logic Locking
Logic obfuscation is introduced as a pivotal defense against multiple hardware threats on Integrated Circuits (ICs), including reverse engineering (RE) and intellectual property (IP) theft.
Deep Multi-attributed Graph Translation with Node-Edge Co-evolution
Then, a spectral graph regularization based on our non-parametric graph Laplacian is proposed in order to learn and maintain the consistency of the predicted nodes and edges.
Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design
HLS tools offer a plethora of techniques to optimize designs for both area and performance, but resource usage and timing reports of HLS tools mostly deviate from the post-implementation results.
An Exhaustive Analysis of Lazy vs. Eager Learning Methods for Real-Estate Property Investment
Based on our study, lazy models like KStar lead to higher accuracy and lower prediction error compared to eager methods like J48 and LR.
Estimating the Circuit Deobfuscating Runtime based on Graph Deep Learning
Deobfuscation runtime could have a large span ranging from few milliseconds to thousands of years or more, depending on the number and layouts of the ICs and camouflaged gates.
