Search Results for author: Roberto DiCecco

Found 2 papers, 1 papers with code

DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration

no code implementations13 Jul 2018 Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane OConnell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu

Overlays have shown significant promise for field-programmable gate-arrays (FPGAs) as they allow for fast development cycles and remove many of the challenges of the traditional FPGA hardware design flow.

Distributed, Parallel, and Cluster Computing Hardware Architecture Signal Processing

Caffeinated FPGAs: FPGA Framework For Convolutional Neural Networks

1 code implementation30 Sep 2016 Roberto DiCecco, Griffin Lacey, Jasmina Vasiljevic, Paul Chow, Graham Taylor, Shawki Areibi

Convolutional Neural Networks (CNNs) have gained significant traction in the field of machine learning, particularly due to their high accuracy in visual recognition.

General Classification

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