Pre-Defined Sparse Neural Networks with Hardware Acceleration

2 code implementations • 4 Dec 2018 • Sourya Dey, Kuan-Wen Huang, Peter A. Beerel, Keith M. Chugg

Neural networks have proven to be extremely powerful tools for modern artificial intelligence applications, but computational and storage complexity remain limiting factors.

A Highly Parallel FPGA Implementation of Sparse Neural Network Training

1 code implementation • 31 May 2018 • Sourya Dey, Diandian Chen, Zongyang Li, Souvik Kundu, Kuan-Wen Huang, Keith M. Chugg, Peter A. Beerel

We demonstrate an FPGA implementation of a parallel and reconfigurable architecture for sparse neural networks, capable of on-chip training and inference.

Characterizing Sparse Connectivity Patterns in Neural Networks

no code implementations • ICLR 2018 • Sourya Dey, Kuan-Wen Huang, Peter A. Beerel, Keith M. Chugg

We propose a novel way of reducing the number of parameters in the storage-hungry fully connected layers of a neural network by using pre-defined sparsity, where the majority of connections are absent prior to starting training.

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