no code implementations • 22 Apr 2024 • Jonas Ney, Christoph Füllner, Vincent Lauinger, Laurent Schmalen, Sebastian Randel, Norbert Wehn
Thus, in this work, we present a high-performance FPGA implementation of an ANN-based equalizer, which meets the throughput requirements of modern optical communication systems.
no code implementations • 23 Feb 2024 • Jonas Ney, Patrick Matalla, Vincent Lauinger, Laurent Schmalen, Sebastian Randel, Norbert Wehn
In this work, we present a high-throughput field programmable gate array (FPGA) demonstrator of an artificial neural network (ANN)-based equalizer.
no code implementations • 17 Jan 2024 • Vincent Lauinger, Patrick Matalla, Jonas Ney, Norbert Wehn, Sebastian Randel, Laurent Schmalen
We demonstrate and evaluate a fully-blind digital signal processing (DSP) chain for 100G passive optical networks (PONs), and analyze different equalizer topologies based on neural networks with low hardware complexity.
no code implementations • 14 Apr 2023 • Jonas Ney, Vincent Lauinger, Laurent Schmalen, Norbert Wehn
In recent years, communication engineers put strong emphasis on artificial neural network (ANN)-based algorithms with the aim of increasing the flexibility and autonomy of the system and its components.
no code implementations • 11 Apr 2023 • Jonas Ney, Bilal Hammoud, Norbert Wehn
In communication systems, Autoencoder (AE) refers to the concept of replacing parts of the transmitter and receiver by artificial neural networks (ANNs) to train the system end-to-end over a channel model.
no code implementations • 15 Sep 2022 • Vincent Lauinger, Manuel Hoffmann, Jonas Ney, Norbert Wehn, Laurent Schmalen
The proposed approach is independent of the equalizer topology and enables the application of powerful neural network based equalizers.
no code implementations • 28 Jun 2021 • Jonas Ney, Dominik Loroch, Vladimir Rybalkin, Nico Weber, Jens Krüger, Norbert Wehn
To efficiently implement DNNs on a specific FPGA platform for a given cost criterion, e. g. energy efficiency, an enormous amount of design parameters has to be considered from the topology down to the final hardware implementation.