no code implementations • 10 Apr 2024 • Muer Tie, Julong Wei, Zhengjun Wang, Ke wu, Shansuai Yuan, Kaizhao Zhang, Jie Jia, Jieru Zhao, Zhongxue Gan, Wenchao Ding
Online construction of open-ended language scenes is crucial for robotic applications, where open-vocabulary interactive scene understanding is required.
no code implementations • 29 Mar 2024 • Ke wu, Kaizhao Zhang, Zhiwei Zhang, Shanshuai Yuan, Muer Tie, Julong Wei, Zijun Xu, Jieru Zhao, Zhongxue Gan, Wenchao Ding
However, integrating 3DGS into a street-view dense mapping framework still faces two challenges, including incomplete reconstruction due to the absence of geometric information beyond the LiDAR coverage area and extensive computation for reconstruction in large urban scenes.
1 code implementation • 14 Jan 2024 • Mingzhe Gao, Jieru Zhao, Zhe Lin, Minyi Guo
High-level synthesis (HLS) notably speeds up the hardware design process by avoiding RTL programming.
no code implementations • 23 Jul 2023 • Guan Shen, Jieru Zhao, Zeke Wang, Zhe Lin, Wenchao Ding, Chentao Wu, Quan Chen, Minyi Guo
Along with the fast evolution of deep neural networks, the hardware system is also developing rapidly.
no code implementations • 2 May 2023 • Wenchao Ding, Jieru Zhao, Yubin Chu, Haihui Huang, Tong Qin, Chunjing Xu, Yuxiang Guan, Zhongxue Gan
However, how to cognize the ``road'' for automated vehicles where there is no well-defined ``roads'' remains an open problem.
no code implementations • 29 Jun 2022 • Guan Shen, Jieru Zhao, Quan Chen, Jingwen Leng, Chao Li, Minyi Guo
However, the quadratic complexity of self-attention w. r. t the sequence length incurs heavy computational and memory burdens, especially for tasks with long sequences.
1 code implementation • 25 Jan 2022 • Zhe Lin, Zike Yuan, Jieru Zhao, Wei zhang, Hui Wang, Yonghong Tian
Specifically, in the graph construction flow, we introduce buffer insertion, datapath merging, graph trimming and feature annotation techniques to transform HLS designs into graph-structured data, which encode both intra-operation micro-architectures and inter-operation interconnects annotated with switching activities.
no code implementations • 5 Jun 2020 • Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei zhang, Shaojie Shen
To reduce the design effort and achieve the right balance, we propose FP-Stereo for building high-performance stereo matching pipelines on FPGAs automatically.
no code implementations • 6 May 2019 • Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei zhang
Early and accurate congestion estimation is of great benefit to guide the optimization in HLS and improve the efficiency of implementation.