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Biologically Plausible Learning on Neuromorphic Hardware Architectures
Using the benchmarking framework DNN+NeuroSim, we investigate the impact of hardware nonidealities and quantization on algorithm performance, as well as how network topologies and algorithm-level design choices can scale latency, energy and area consumption of a chip.
Neuromorphic Algorithm-hardware Codesign for Temporal Pattern Learning
This circuit implementation of the neuron model is simulated to demonstrate its ability to react to temporal spiking patterns with an adaptive threshold.
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