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Found 9 papers, 2 papers with code
GCV-Turbo: End-to-end Acceleration of GNN-based Computer Vision Tasks on FPGA
Moreover, GCV-Turbo supports the execution of the standalone CNNs or GNNs, achieving performance comparable to that of state-of-the-art CNN (GNN) accelerators for widely used CNN-only (GNN-only) models.
VTR: An Optimized Vision Transformer for SAR ATR Acceleration on FPGA
We directly train this model on SAR datasets which have limited training samples to evaluate its effectiveness for SAR ATR applications.
Accelerating ViT Inference on FPGA through Static and Dynamic Pruning
For algorithm design, we systematically combine a hardware-aware structured block-pruning method for pruning model parameters and a dynamic token pruning method for removing unimportant token vectors.
A Single Graph Convolution Is All You Need: Efficient Grayscale Image Classification
Our experimental results on benchmark grayscale image datasets demonstrate the effectiveness of the proposed model, achieving vastly lower latency (up to 16$\times$ less) and competitive or leading performance compared to other state-of-the-art image classification models on various domain-specific grayscale image classification datasets.
Ranked #16 on
Image Classification
on Fashion-MNIST
PAHD: Perception-Action based Human Decision Making using Explainable Graph Neural Networks on SAR Images
This detailed information includes the SAR image features that contributed to the classification, the classification confidence, and the probability of the identified object being classified as a different object type or class.
Exploiting On-chip Heterogeneity of Versal Architecture for GNN Inference Acceleration
To exploit data sparsity during inference, we devise a runtime kernel mapping strategy that dynamically assigns computation tasks to the PL and AIE based on data sparsity.
Graph Neural Network for Accurate and Low-complexity SAR ATR
In this work, we propose a graph neural network (GNN) model to achieve accurate and low-latency SAR ATR.
Accurate, Low-latency, Efficient SAR Automatic Target Recognition on FPGA
Compared with the state-of-the-art CNNs, the proposed GNN achieves comparable accuracy with $1/3258$ computation cost and $1/83$ model size.
Model-Architecture Co-Design for High Performance Temporal GNN Inference on FPGA
Taking advantage of the model optimizations, we propose a principled hardware architecture using batching, pipelining, and prefetching techniques to further improve the performance.
