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Found 12 papers, 2 papers with code
NAX: Co-Designing Neural Network and Hardware Architecture for Memristive Xbar based Computing Systems
The hardware efficiency (energy, latency and area) as well as application accuracy (considering device and circuit non-idealities) of DNNs mapped to such hardware are co-dependent on network parameters, such as kernel size, depth etc.
GENIEx: A Generalized Approach to Emulating Non-Ideality in Memristive Xbars using Neural Networks
Further, using the functional simulator and GENIEx, we demonstrate that an analytical model can overestimate the degradation in classification accuracy by $\ge 10\%$ on CIFAR-100 and $3. 7\%$ on ImageNet datasets compared to GENIEx.
Emerging Technologies
SPACE: Structured Compression and Sharing of Representational Space for Continual Learning
A minimal number of extra dimensions required to explain the current task are added to the Core space and the remaining Residual is freed up for learning the next task.
PABO: Pseudo Agent-Based Multi-Objective Bayesian Hyperparameter Optimization for Efficient Neural Accelerator Design
The ever increasing computational cost of Deep Neural Networks (DNN) and the demand for energy efficient hardware for DNN acceleration has made accuracy and hardware cost co-optimization for DNNs tremendously important, especially for edge devices.
Constructing Energy-efficient Mixed-precision Neural Networks through Principal Component Analysis for Edge Intelligence
The `Internet of Things' has brought increased demand for AI-based edge computing in applications ranging from healthcare monitoring systems to autonomous vehicles.
Efficient Hybrid Network Architectures for Extremely Quantized Neural Networks Enabling Intelligence at the Edge
In this work, we propose extremely quantized hybrid network architectures with both binary and full-precision sections to emulate the classification performance of full-precision networks while ensuring significant energy efficiency and memory compression.
PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference
We also present the PUMA compiler which translates high-level code to PUMA ISA.
Emerging Technologies Hardware Architecture
Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays
In this paper, we demonstrate how deep binary networks can be accelerated in modified von-Neumann machines by enabling binary convolutions within the SRAM array.
Emerging Technologies
Incremental Learning in Deep Convolutional Neural Networks Using Partial Network Sharing
We propose an efficient training methodology and incrementally growing DCNN to learn new tasks while sharing part of the base network.
TraNNsformer: Neural network transformation for memristive crossbar based neuromorphic system design
Implementation of Neuromorphic Systems using post Complementary Metal-Oxide-Semiconductor (CMOS) technology based Memristive Crossbar Array (MCA) has emerged as a promising solution to enable low-power acceleration of neural networks.
RESPARC: A Reconfigurable and Energy-Efficient Architecture with Memristive Crossbars for Deep Spiking Neural Networks
In this paper, we propose RESPARC - a reconfigurable and energy efficient architecture built-on Memristive Crossbar Arrays (MCA) for deep Spiking Neural Networks (SNNs).
FALCON: Feature Driven Selective Classification for Energy-Efficient Image Recognition
We evaluate our approach for a 12-object classification task on the Caltech101 dataset and 10-object task on CIFAR-10 dataset by constructing FALCON models on the NeuE platform in 45nm technology.
