Search Results for author:
Found 42 papers, 11 papers with code
H3DFact: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations
Disentangling attributes of various sensory signals is central to human-like perception and reasoning and a critical task for higher-order cognitive and neuro-symbolic AI systems.
Abstracting Sparse DNN Acceleration via Structured Sparse Tensor Decomposition
Next, we develop a software framework, TASDER, to accelerate DNNs by searching layer-wise, high-quality structured decomposition for both weight and activation tensors so that they can be accelerated by any systems with structured sparse hardware support.
Algorithm-Hardware Co-Design of Distribution-Aware Logarithmic-Posit Encodings for Efficient DNN Inference
Traditional Deep Neural Network (DNN) quantization methods using integer, fixed-point, or floating-point data types struggle to capture diverse DNN parameter distributions at low precision, and often require large silicon overhead and intensive quantization-aware training.
GEAR: An Efficient KV Cache Compression Recipe for Near-Lossless Generative Inference of LLM
Key-value (KV) caching has become the de-facto to accelerate generation speed for large language models (LLMs) inference.
Progressive Gradient Flow for Robust N:M Sparsity Training in Transformers
In this work, we study the effectiveness of existing sparse training recipes at \textit{high-sparsity regions} and argue that these methods fail to sustain the model quality on par with low-sparsity regions.
Towards Cognitive AI Systems: a Survey and Prospective on Neuro-Symbolic AI
The remarkable advancements in artificial intelligence (AI), primarily driven by deep neural networks, have significantly impacted various aspects of our lives.
Subgraph Stationary Hardware-Software Inference Co-Design
For the stream of queries, SUSHI yields up to 25% improvement in latency, 0. 98% increase in served accuracy.
Chakra: Advancing Performance Benchmarking and Co-design using Standardized Execution Traces
Benchmarking and co-design are essential for driving optimizations and innovation around ML models, ML software, and next-generation hardware.
TACOS: Topology-Aware Collective Algorithm Synthesizer for Distributed Machine Learning
To this end, this paper introduces TACOS, an automated synthesizer that generates topology-aware collective algorithms for common distributed machine learning collectives across arbitrary input network topologies.
Perspectives on AI Architectures and Co-design for Earth System Predictability
This paper discusses the topic of the `AI Architectures and Co-design' session and associated outcomes.
ASTRA-sim2.0: Modeling Hierarchical Networks and Disaggregated Systems for Large-model Training at Scale
In this paper, we extend the open-source ASTRA-sim infrastructure and endow it with the capabilities to model state-of-the-art and emerging distributed training models and platforms.
VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs
Therefore, as DL workloads embrace sparsity to reduce the computations and memory size of models, it is also imperative for CPUs to add support for sparsity to avoid under-utilization of the dense matrix engine and inefficient usage of the caches and registers.
COMET: A Comprehensive Cluster Design Methodology for Distributed Deep Learning Training
To facilitate the design space exploration of such massive DL training clusters, we introduce COMET, a holistic cluster design methodology and workflow to jointly study the impact of parallelization strategies and key cluster resource provisioning on the performance of distributed DL training.
XRBench: An Extended Reality (XR) Machine Learning Benchmark Suite for the Metaverse
We hope that our work will stimulate research and lead to the development of a new generation of ML systems for XR use cases.
Demystifying Map Space Exploration for NPUs
Map Space Exploration is the problem of finding optimized mappings of a Deep Neural Network (DNN) model on an accelerator.
Training Recipe for N:M Structured Sparsity with Decaying Pruning Mask
In this work, we focus on N:M sparsity and extensively study and evaluate various training recipes for N:M sparsity in terms of the trade-off between model accuracy and compute cost (FLOPs).
Impact of RoCE Congestion Control Policies on Distributed Training of DNNs
Our results indicate that previously proposed RoCE congestion control schemes have little impact on the end-to-end performance of training workloads, motivating the necessity of designing an optimized, yet low-overhead, congestion control scheme based on the characteristics of distributed training platforms and workloads.
DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators
The design of DNN accelerators includes two key parts: HW resource configuration and mapping strategy.
DNNFuser: Generative Pre-Trained Transformer as a Generalized Mapper for Layer Fusion in DNN Accelerators
Dataflow/mapping decides the compute and energy efficiency of DNN accelerators.
Themis: A Network Bandwidth-Aware Collective Scheduling Policy for Distributed Training of DL Models
Distributed training is a solution to reduce DNN training time by splitting the task across multiple NPUs (e. g., GPU/TPU).
RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU
As AI-based applications become pervasive, CPU vendors are starting to incorporate matrix engines within the datapath to boost efficiency.
Exploring Multi-dimensional Hierarchical Network Topologies for Efficient Distributed Training of Trillion Parameter DL Models
High-performance distributed training platforms should leverage multi-dimensional hierarchical networks, which interconnect accelerators through different levels of the network, to dramatically reduce expensive NICs required for the scale-out network.
Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operations on Spatial Accelerators
The algorithms and accelerator cost models are connected via a novel mapping abstraction that captures the map space of spatial accelerators which can be systematically pruned based on constraints from the hardware, workload, and mapper.
AIRCHITECT: Learning Custom Architecture Design and Mapping Space
We design and train a custom network architecture called AIRCHITECT, which is capable of learning the architecture design space with as high as 94. 3% test accuracy and predicting optimal configurations which achieve on average (GeoMean) of 99. 9% the best possible performance on a test dataset with $10^5$ GEMM workloads.
FLAT: An Optimized Dataflow for Mitigating Attention Bottlenecks
In contrast, FLAT unblocks transformer models for inputs with up to 64K elements
Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication
There is a growing interest in custom spatial accelerators for machine learning applications.
MAGMA: An Optimization Framework for Mapping Multiple DNNs on Multiple Accelerator Cores
In particular, we focus on the problem of mapping jobs from several DNNs simultaneously on an accelerator.
Self-Adaptive Reconfigurable Arrays (SARA): Using ML to Assist Scaling GEMM Acceleration
We demonstrate an instance of SARA with an accelerator we call SAGAR, which introduces a novel reconfigurable systolic array that can be configured to work as a distributed collection of smaller arrays of various sizes or as a single array with flexible aspect ratios.
ConfuciuX: Autonomous Hardware Resource Assignment for DNN Accelerators using Reinforcement Learning
We also augment the RL approach with a genetic algorithm for further fine-tuning.
CLAN: Continuous Learning using Asynchronous Neuroevolution on Commodity Edge Devices
The true impact of AI can only be fully realized if we can have AI agents continuously interacting with the real world and solving everyday problems.
Restructuring, Pruning, and Adjustment of Deep Models for Parallel Distributed Inference
In this paper, we consider the parallel implementation of an already-trained deep model on multiple processing nodes (a. k. a.
The gem5 Simulator: Version 20.0+
The open-source and community-supported gem5 simulator is one of the most popular tools for computer architecture research.
Hardware Architecture
STONNE: A Detailed Architectural Simulator for Flexible Neural Network Accelerators
The design of specialized architectures for accelerating the inference procedure of Deep Neural Networks (DNNs) is a booming area of research nowadays.
Generative Design of Hardware-aware DNNs
We propose a new way for autonomous quantization and HW-aware tuning.
Conditional Neural Architecture Search
Designing resource-efficient Deep Neural Networks (DNNs) is critical to deploy deep learning solutions over edge platforms due to diverse performance, power, and memory budgets.
Marvel: A Data-centric Compiler for DNN Operators on Spatial Accelerators
Searching for the optimal mappings is challenging because of the large space of mappings, and this challenge gets exacerbated with new operators and diverse accelerator configurations. To address this challenge, we propose a decoupled off-chip/on-chip approach that decomposes the mapping space into off-chip and on-chip subspaces, and first optimizes the off-chip subspace followed by the on-chip subspace.
Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks
Neural Architecture Search (NAS) has demonstrated its power on various AI accelerating platforms such as Field Programmable Gate Arrays (FPGAs) and Graphic Processing Units (GPUs).
Heterogeneous Dataflow Accelerators for Multi-DNN Workloads
The results suggest that HDA is an alternative class of Pareto-optimal accelerators to RDA with strength in energy, which can be a better choice than RDAs depending on the use cases.
Distributed, Parallel, and Cluster Computing
Reinforcement Learning based Interconnection Routing for Adaptive Traffic Optimization
In this work, we demonstrate the promise of applying reinforcement learning (RL) to optimize NoC runtime performance.
SCALE-Sim: Systolic CNN Accelerator
Systolic Arrays are one of the most popular compute substrates within Deep Learning accelerators today, as they provide extremely high efficiency for running dense matrix multiplications.
Distributed, Parallel, and Cluster Computing Hardware Architecture
GeneSys: Enabling Continuous Learning through Neural Network Evolution in Hardware
EvE can evolve the topology and weights of neural networks completely in hardware for the task at hand, without requiring hand-optimization or backpropagation training.
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach Using MAESTRO
The data partitioning and scheduling strategies used by DNN accelerators to leverage reuse and perform staging are known as dataflow, and they directly impact the performance and energy efficiency of DNN accelerator designs.
