no code implementations • 12 Jul 2022 • Fei Hua, Yuwei Jin, Ang Li, Chenxu Liu, Meng Wang, Yanhao Chen, Chi Zhang, Ari Hayes, Samuel Stein, Minghao Guo, Yipeng Huang, Eddy Z. Zhang
Evaluations through simulation and on real IBM-Q devices show that our framework can significantly reduce the error rate by up to 6$\times$, with only $\sim$60\% circuit depth compared to state-of-the-art gate scheduling approaches.