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Found 10 papers, 4 papers with code
Heterogeneous Encoders Scaling In The Transformer For Neural Machine Translation
Although the Transformer is currently the best-performing architecture in the homogeneous configuration (self-attention only) in Neural Machine Translation, many State-of-the-Art models in Natural Language Processing are made of a combination of different Deep Learning approaches.
A request for clarity over the End of Sequence token in the Self-Critical Sequence Training
The Image Captioning research field is currently compromised by the lack of transparency and awareness over the End-of-Sequence token (<Eos>) in the Self-Critical Sequence Training.
Exploiting Multiple Sequence Lengths in Fast End to End Training for Image Captioning
We introduce a method called the Expansion mechanism that processes the input unconstrained by the number of elements in the sequence.
Ranked #1 on
Image Captioning
on MS COCO
Exploring the sequence length bottleneck in the Transformer for Image Captioning
Most recent state of the art architectures rely on combinations and variations of three approaches: convolutional, recurrent and self-attentive methods.
A TinyML Platform for On-Device Continual Learning with Quantized Latent Replays
In this work, we introduce a HW/SW platform for end-to-end CL based on a 10-core FP32-enabled parallel ultra-low-power (PULP) processor.
Leveraging Automated Mixed-Low-Precision Quantization for tiny edge microcontrollers
The severe on-chip memory limitations are currently preventing the deployment of the most accurate Deep Neural Network (DNN) models on tiny MicroController Units (MCUs), even if leveraging an effective 8-bit quantization scheme.
Robustifying the Deployment of tinyML Models for Autonomous mini-vehicles
We leverage a family of compact and high-throughput tinyCNNs to control the mini-vehicle, which learn in the target environment by imitating a computer vision algorithm, i. e., the expert.
Memory-Driven Mixed Low Precision Quantization For Enabling Deep Network Inference On Microcontrollers
To fit the memory and computational limitations of resource-constrained edge-devices, we exploit mixed low-bitwidth compression, featuring 8, 4 or 2-bit uniform quantization, and we model the inference graph with integer-only operations.
HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA
Heterogeneous embedded systems on chip (HESoCs) co-integrate a standard host processor with programmable manycore accelerators (PMCAs) to combine general-purpose computing with domain-specific, efficient processing capabilities.
Hardware Architecture Distributed, Parallel, and Cluster Computing
NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs
Deep convolutional neural networks (CNNs) obtain outstanding results in tasks that require human-level understanding of data, like image or speech recognition.
